2 Commits

Author	SHA1	Message	Date
Dhanya Thattil	6e14a2efe2	ctb fix: reset pll reset also adc and dbit phase (fixed), also required adcs to be configured again(due to adc clock being stopped temporarily	2019-06-17 17:24:59 +02:00
Dhanya Thattil	89a06f099c	merging refactor (replacing)	2019-04-12 10:53:09 +02:00