9198 Commits

Author SHA1 Message Date
dc85a48864 update xilinxCtb pattern bit mapping
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2025-03-27 18:03:02 +01:00
dc8a34592a started pattern docu 2025-03-27 17:03:36 +01:00
96ae1a1cca found bug needed to refresh member variables
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2025-03-20 16:47:42 +01:00
3793e7b7d4 solved merge conflict 2025-03-20 16:16:35 +01:00
713e4f6822 added dbitreorder flag to chip test board gui 2025-03-20 16:12:01 +01:00
Fröjd Lars Erik
fada23365e added workflow for python lib
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2025-03-20 13:56:46 +01:00
Fröjd Lars Erik
6dd0a5b0dd added zlib 2025-03-20 13:39:51 +01:00
Fröjd Lars Erik
c3b197f209 removed conda build pin 2025-03-20 13:28:46 +01:00
Fröjd Lars Erik
9f49ac6457 fixed typo 2025-03-20 13:12:42 +01:00
Fröjd Lars Erik
0b3ead6353 conda build of main library 2025-03-20 13:10:27 +01:00
8b3625fc01 added dbitreorder flag to chip test board gui
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2025-03-20 11:00:40 +01:00
Fröjd Lars Erik
0da508a8b7 added back some python versions
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2025-03-19 22:05:19 +01:00
Fröjd Lars Erik
608eb1a436 cleaned meta yaml 2025-03-19 22:03:22 +01:00
Fröjd Lars Erik
c0bc6fe25a Merge branch 'dev/scikitbuild' of github.com:slsdetectorgroup/slsDetectorPackage into dev/scikitbuild 2025-03-19 22:00:00 +01:00
Fröjd Lars Erik
a0d540fd72 restored comments, cleanup 2025-03-19 21:59:30 +01:00
Erik Fröjdh
46a46b65e5
Merge branch 'developer' into dev/scikitbuild 2025-03-19 21:53:29 +01:00
Fröjd Lars Erik
4f62b1a05c separated the recipes 2025-03-19 21:49:12 +01:00
45dadf8b90
Merge pull request #1163 from slsdetectorgroup/dev/fix_tests_real_g2
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dev: fixed tests for real gotthard2. change in reg address to test
2025-03-19 17:16:00 +01:00
e8e84a4e72 fixed tests for real gotthard2. change in reg address to test 2025-03-19 17:12:21 +01:00
Fröjd Lars Erik
2f390971e6 WI{ 2025-03-19 16:37:37 +01:00
b7e17d1320 added reorder to documentation, added flag to master binary and hdf5 file
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2025-03-19 11:51:28 +01:00
c54b1cb6af clang format 2025-03-19 08:37:07 +01:00
ddb89bce34 Merge branch 'dev/issue_dont_reorder_digital_data' of github.com:slsdetectorgroup/slsDetectorPackage into dev/issue_dont_reorder_digital_data 2025-03-19 08:24:33 +01:00
f056f9d31b reserved enough size in the fifo buffer to reorder all added proper 4 byte alignment 2025-03-18 21:42:34 +01:00
froejdh_e
d9a50ad9f4 WIP 2025-03-18 13:21:46 +01:00
ce0450d498
Merge pull request #1158 from slsdetectorgroup/dev/jf_timing_decoder_only_hw2.0
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get timin g info decoder not supported for jf 2.0
2025-03-18 12:35:23 +01:00
7b531059a0 even get is not supported for timing info decoder for jungfrau hw v1.0. only hw v2.0 is uspported 2025-03-18 12:33:07 +01:00
froejdh_e
bc187bb198 moved compiled extension into slsdet 2025-03-18 10:56:03 +01:00
froejdh_e
eb8c34f53b skeleton pyproject.toml 2025-03-18 10:33:51 +01:00
d9a50705e4
Merge pull request #1148 from slsdetectorgroup/dev/cmd_for_ctb_reorder
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Dev/cmd for ctb reorder
2025-03-17 17:10:52 +01:00
f4626c2c81 fix tests from merge 2025-03-17 15:45:59 +01:00
e0a48e1e75 implemented proper alignment in reorder function before casting to uint64_t ptr 2025-03-17 15:39:31 +01:00
ec4eb1978e merge fix from dev/issue_dont_reorder_digital_data 2025-03-17 15:28:22 +01:00
842b376801 fixed rx_dbitreorder cmd line tests 2025-03-17 15:23:02 +01:00
13b2cada66 ctb reorder default being true in dataprocessor 2025-03-17 15:20:40 +01:00
Erik Fröjdh
3c2f149c22
Adding patterntools to slsdet (#1142)
* added patterntools from mythen3tools
* refactored do use implementation from slsSupportLib
2025-03-17 08:46:26 +01:00
0a5b5aac4b added unit tests for dataprocessor rearranging functions 2025-03-14 14:04:55 +01:00
6e5b058fc1 merge fix 2025-03-13 13:17:54 +01:00
ace2b3a938 Merge branch 'dev/issue_dont_reorder_digital_data' into dev/cmd_for_ctb_reorder 2025-03-13 13:16:29 +01:00
5a8213024e
Merge pull request #1145 from slsdetectorgroup/dev/xilinx_ctb_api
add xilinx ctb api to --versions command
2025-03-13 13:15:04 +01:00
bd66228b30 minor to check workflow 2025-03-13 11:14:01 +01:00
e1c9754cd2 Added test for rx_dbitreorder command 2025-03-12 17:31:37 +01:00
ff101e19cd added pybind for it 2025-03-12 17:31:33 +01:00
e8ac048114 ctb: added command 'rx_dbitreorder' that sets a flag in the receiver to set the reorder flag. By default it is 1. Setting to false means 'do not reorder' and to keep what the board spits out, which is that all signals in a sample are grouped together 2025-03-12 17:31:20 +01:00
3c79e8d7b2 trailing bits are removed even if reorder false and bitlist empty 2025-03-12 16:38:18 +01:00
a74fb2bcd1 added function Reorder 2025-03-12 16:12:00 +01:00
63bb79d727 added first rather generic test for Rearrange Function, could be changed to a parametrized test 2025-03-12 10:51:18 +01:00
8d87a6ee4e used clang-formating 2025-03-11 16:32:31 +01:00
ab01940769 add xilinx ctb api to --versions command 2025-03-11 15:51:46 +01:00
23aa9c2814 added reorder variable, changed function ArrangeDBitData to support reordering and no reordering. Moved transceiver data such that it is contiguous with rearranged digital data 2025-03-11 12:07:10 +01:00