* put back code to obtain adc and dac device indexafter loading device tree and then create folder iio_device_links and create symbolic links there according to device indices found. ln -sf operation not permitted, so folder has to be deleted and created everytime. Also refactored definitions to have all the xilinx name or detector specific stuff out of programbyArm.c
* uncommented waittransceiverreset at startup (should work now) and return of powering off chip at startup (error for transceiver alignment reset)
* updated registerdefs from firmware
* minor prints and updating names from registerdefs
* waittransceiverreset has been fixed in firmware and removing warnign for that, transceiver alignment check for powering off chip is not done in fw (giving a warning and returning ok for now)
* fixing ipchecksum (not done), removed startperiphery, allowing readout command to be allowed for xilinx when acquiring
* period and exptime(patternwaittime level 0)
* added new regsieterdefs and updated api version and fixedpattern reg
* autogenerate commands
* formatting
* minor
* wip resetflow, readout mode, transceiver mask, transceiver enable
* acquisition, but streaming done bit and busy (exposing + read chip to fifo) not known yet from fw
* programming fpga and device tree done
* most configuration done, need to connect configuretransceiver to client
* stuck at resetting transciever timed out
* minor
* fixed virtual, added chip busyto fifo, streaming busy, set/getnext framenumber
* configuretransceiver from client, added help in client
* make formatt and command generation
* tests for xilinx ctb works
* command generation
* dacs added and tested, power not done
* power added
* added temp_fpga
* binaries in
* ctrlreg is 0 to enable chip=fixed, high dac val = min val= fixed, power regulators in weird order=fixed, device tree could be loaded with dacs before adcs=fixed
* start works
* virtual server sends
* receiver works
* tests
* python function and enum generation, commands generatorn and autocomplete, formatting, tests
* tests fail at start(transceiver not aligned)
* tests passed
* all binaries compiled
* eiger binary in
* added --nomodule cehck for xilinx
* implemented testbus, testfpga, set/get #frames, triggers, allowed that and for connection to client, also allowed, getnumchannels, configuremac, getrunstatus, setdetectorposition with dummy values
* connected kernelversion, hardwareversion, versions, framesl, triggersl, dr, timingmode, pattern (except patioctrl) thats there for altera ctb
* replaced set/get64Bit to set/getU64bit in all loadpattern.c for (ctb and m3 also)
* updated registers, arm64
* compiler set to aarch64 for xilinx server
* updated RegisterDefs.h
* merge into generate branch and resolving conflicts and adding the xilinx changes to callerspecial and commands.yaml
* compiles and can print firmware version (using a different csp0 address)
* fixing other servers (gotthard, jungfrau, moench, mythen3) that it returns in case of mapping failure, xilinxctb: added that it checks type, prints proper fw version, checks kernel date, added armprocessor define to use in common places, added specifiers to supress overflow and truncation warnings
* added detector ip and mac adddress to the printout
* fixed tests and recompiled servers
