* period and exptime(patternwaittime level 0)
* added new regsieterdefs and updated api version and fixedpattern reg
* autogenerate commands
* formatting
* minor
* wip resetflow, readout mode, transceiver mask, transceiver enable
* acquisition, but streaming done bit and busy (exposing + read chip to fifo) not known yet from fw
* programming fpga and device tree done
* most configuration done, need to connect configuretransceiver to client
* stuck at resetting transciever timed out
* minor
* fixed virtual, added chip busyto fifo, streaming busy, set/getnext framenumber
* configuretransceiver from client, added help in client
* make formatt and command generation
* tests for xilinx ctb works
* command generation
* dacs added and tested, power not done
* power added
* added temp_fpga
* binaries in
* ctrlreg is 0 to enable chip=fixed, high dac val = min val= fixed, power regulators in weird order=fixed, device tree could be loaded with dacs before adcs=fixed
* start works
* virtual server sends
* receiver works
* tests
* python function and enum generation, commands generatorn and autocomplete, formatting, tests
* tests fail at start(transceiver not aligned)
* tests passed
* all binaries compiled
* eiger binary in
* added --nomodule cehck for xilinx
* transceiverenable, tsamples, romode for tranceiver and digital_transceiver
* 202 spec instr only for transceiver mode
* removed check for empty in trans readout and clean memory before reading from fifo
* ctb read fifo strobe for all after reading all channels, adding 1us after selecting channel, changing fw date
* updated 10gb transceiver enable
----
* added transceiver (tsamples, romode(transceiver, digital_transceiver), transceiverenable (mask)
* clean memory before reading from fifo (for analog and digital as well)
* read fifo then read strobe (also corresp fw) fixes number of reads (also for analg and digital)-> increases all pipelines by 1
* fixed bug in rearranging digital data in receiver
* fixed bug in streaming size of data after rearranging
* fixed bug in setbit, clearbit,and getbit
* status checks fifo before returning idle (transmitting if data in fifo if transceiver more enabled)
* soem matterhorn specifics that will need to be put into pattern in a month or two. this is temporary.
* NOTE: breaking api. rxParameters struct has transceiverenabel and tsamples given from det to receiver
* initital implementation
* datetime replaces with sls::Duration in Python C bindings
* using custom type caster
* fix for conversion to seconds
* added set_count in python
* common header for pybind11 includes
authored-by: Erik Frojdh <erik.frojdh@psi.ch>
* wip, adding m3 functions: polarity, inerpolation, pumpprobe
* added interpol, polarity, pump probe, analog pulsing, digital pulsing
* tests
* binaries in
* update release
* added python polarity enum
* fixed python and minor readability in mythen3.c
* binarie sin
* added all the m3 funcs also in list.c and enablingall counters for enabling interpolation
* binarie sin
* Setting pattern from memory (#218)
* ToString accepts c-style arrays
* fixed patwait time bug in validation
* Introduced pattern class
* compile for servers too
* Python binding for Pattern
* added scanParameters in Python
* slsReceiver: avoid potential memory leak around Implementation::generalData
* additional constructors for scanPrameters in python
* bugfix: avoid potentital memory leak in receiver if called outside constructor context
* added scanParameters in Python
* additional constructors for scanPrameters in python
* M3defaultpattern (#227)
* default pattern for m3 and moench including Python bindings
* M3settings (#228)
* some changes to compile on RH7 and in the server to load the default chip status register at startup
* Updated mythen3DeectorServer_developer executable with correct initialization at startup
Co-authored-by: Erik Frojdh <erik.frojdh@gmail.com>
Co-authored-by: Anna Bergamaschi <anna.bergamaschi@psi.ch>
* Pattern.h as a public header files (#229)
* fixed buffer overflow but caused by using global instead of local enum
* replacing out of range trimbits with edge values
* replacing dac values that are out of range after interpolation
* updated pybind11 to 2.6.2
* Mythen3 improved synchronization (#231)
Disabling scans for multi module Mythen3, since there is no feedback of the detectors being ready
startDetector first starts the slaves then the master
acquire firs calls startDetector for the slaves then acquire on the master
getMaster to read back from hardware which one is master
* New server for JF to go with the new FW (#232)
* Modified Jungfrau speed settings for HW1.0 - FW fix version 1.1.1, compilation date 210218
* Corrected bug. DBIT clk phase is implemented in both HW version 1.0 and 2.0. Previous version did not update the DBIT phase shift on the configuration of a speed.
* fix for m3 scan with single module
* m3 fw version
* m3 server
* bugfix for bottom when setting quad
* new strategy for finding zmq based on cppzmq
Co-authored-by: Dhanya Thattil <dhanya.thattil@psi.ch>
Co-authored-by: Dhanya Thattil <33750417+thattil@users.noreply.github.com>
Co-authored-by: Alejandro Homs Puron <ahoms@esrf.fr>
Co-authored-by: Anna Bergamaschi <anna.bergamaschi@psi.ch>
Co-authored-by: Xiaoqiang Wang <xiaoqiangwang@gmail.com>
Co-authored-by: lopez_c <carlos.lopez-cuenca@psi.ch>
* ToString accepts c-style arrays
* added patternParameters to python
* fixed patwait time bug in validation
* moved load from file function to patterParameters
* server using patternparamters structure to get pattern
Co-authored-by: Erik Frojdh <erik.frojdh@gmail.com>
