4 Commits

Author	SHA1	Message	Date
Dhanya Thattil	be50344b45	set clock divider, phase and get clock freq for gotthard2, priliminary	2019-10-17 16:39:41 +02:00
Marie Andrä	6e6fcec698	MY3.0:read and write Registers, frames, cycles, delay (#64) ... * MY3.0:read and write Registers, frames, cycles, delay * write pattern seems to work * done all corrections. added default clks: run_clk=125MHz, tick_clk=20MHz (fix), sampling_clk=80MHz (from Carlos) * clk check for aquistition time * clk check for aquistition time * Update slsDetectorServer_defs.h * Update slsDetectorFunctionList.c	2019-09-30 14:36:33 +02:00
Dhanya Thattil	288b59d292	gotthard2 changes for first firmware version	2019-09-26 14:10:11 +02:00
Dhanya Thattil	8c15b52b87	nios	2019-08-30 17:28:18 +02:00