1 Commits

Author	SHA1	Message	Date
Dhanya Thattil	8d185988c1	8.0.2.rc: m3 clkdiv0 20 (#923) ... * m3: clk 0 changed from 10 to 20 (100MHz to 50MHz) * g2: startup clk div back to 10 as in firmware but setting in software startup to 20	2024-07-25 17:17:20 +02:00