- removed feb reset in stop acquisition as it caused processing bit to randomly not go high (leads to infinite loop waiting for it to go high). This is anyway done at prepare acquisition and set trimbits.
- left AND right registers monitored for processing bit done
- febProcessinginprogress returns STATUS_IDLE and not IDLE
- In feb stop acquisition, if processing bit is running forever, checks for 1 s, then if acq done bit is high, returns ok, else throws
- feb stop acquisition returns 1 if success and fucntion in list calling it compares properly instead of STATUS_IDLE (no effect, but incorrect logic)
- chipsignals to trimquad should only monitor right fpga (not both as it will throw)
- fixed error messages of readregister inconsistent values
- setmodule and read frame was returning fail without setting error messages (leading to broken tcp connection due to no error message)
-
* Setting pattern from memory (#218)
* ToString accepts c-style arrays
* fixed patwait time bug in validation
* Introduced pattern class
* compile for servers too
* Python binding for Pattern
* added scanParameters in Python
* slsReceiver: avoid potential memory leak around Implementation::generalData
* additional constructors for scanPrameters in python
* bugfix: avoid potentital memory leak in receiver if called outside constructor context
* added scanParameters in Python
* additional constructors for scanPrameters in python
* M3defaultpattern (#227)
* default pattern for m3 and moench including Python bindings
* M3settings (#228)
* some changes to compile on RH7 and in the server to load the default chip status register at startup
* Updated mythen3DeectorServer_developer executable with correct initialization at startup
Co-authored-by: Erik Frojdh <erik.frojdh@gmail.com>
Co-authored-by: Anna Bergamaschi <anna.bergamaschi@psi.ch>
* Pattern.h as a public header files (#229)
* fixed buffer overflow but caused by using global instead of local enum
* replacing out of range trimbits with edge values
* replacing dac values that are out of range after interpolation
* updated pybind11 to 2.6.2
* Mythen3 improved synchronization (#231)
Disabling scans for multi module Mythen3, since there is no feedback of the detectors being ready
startDetector first starts the slaves then the master
acquire firs calls startDetector for the slaves then acquire on the master
getMaster to read back from hardware which one is master
* New server for JF to go with the new FW (#232)
* Modified Jungfrau speed settings for HW1.0 - FW fix version 1.1.1, compilation date 210218
* Corrected bug. DBIT clk phase is implemented in both HW version 1.0 and 2.0. Previous version did not update the DBIT phase shift on the configuration of a speed.
* fix for m3 scan with single module
* m3 fw version
* m3 server
* bugfix for bottom when setting quad
* new strategy for finding zmq based on cppzmq
Co-authored-by: Dhanya Thattil <dhanya.thattil@psi.ch>
Co-authored-by: Dhanya Thattil <33750417+thattil@users.noreply.github.com>
Co-authored-by: Alejandro Homs Puron <ahoms@esrf.fr>
Co-authored-by: Anna Bergamaschi <anna.bergamaschi@psi.ch>
Co-authored-by: Xiaoqiang Wang <xiaoqiangwang@gmail.com>
Co-authored-by: lopez_c <carlos.lopez-cuenca@psi.ch>
