* roi structure expanded to have ymin and ymax
* compile with 'detector roi'
* wip
* wip, rx_roi, rx_clearroi
* wip rxroi
* rxroi wip
* wip rxroi
* merge fix
* wip
* rx_roi works, impl wip, test
* tests in, impl left
* wip, rxroi impl
* wip, rxroi impl
* wip
* setrx_Roi works, getrx_roi, wip
* rx_roi impl done
* wip, rxroi
* wip, getrx_roi rxr ports
* fix ports
* wip
* wip
* fix positions on server side
* wip
* numports wip
* wip
* jungfrau top inner interface row increment
* x, y detpos, wip
* removed eiger row indices flipping in gui (bottom flipping maintained)
* wip
* wip, jungfrau numinterfaces2
* jungfrau virtual works
* eiger, jungfrau, g2 virtual server works
* eiger positions fix, wip
* binaries in
* minor printout
* binaries in
* merge fix
* merge fix
* removing getposition
* setrxroi wip
* set upto port
* get messed, wip
* roi multi to module works, wip
* wip
* roi dont return -1
* added rxroi metadata in master file
* added rxroifromshm, not yet in detector
* rx roi in gui with box, also for gap pixels (gappixels for jungfrau mess)
* fix for segfault in gui with detaching roi box in gui
* wip
* m3 gui: slave timing modes should be discarded when squashing
* fixed m3 virtual data, and fixed counters in gui asthetics
* m3 roi works
* wip, g2
* wip
* handling g225um boards, and showing roi for gainplot as well
* udpate python functions
* fix for 1d and a2d roi written
* fixed actual roi written to file
* no virtual hdf5 when handling rx roi
* test
* minor
* binarie in
* inconsistent copy with generalData and implementation members, especially for m3 (non default rxr generic values), issue caught on second configure with non m3 default values, eg tengiga 0
* removing test
* wip, adding m3 functions: polarity, inerpolation, pumpprobe
* added interpol, polarity, pump probe, analog pulsing, digital pulsing
* tests
* binaries in
* update release
* added python polarity enum
* fixed python and minor readability in mythen3.c
* binarie sin
* added all the m3 funcs also in list.c and enablingall counters for enabling interpolation
* binarie sin
# Setting DAC names for CTB
* Introduced new shared memory for CTB only
* Prepared for additional functionality
* Works from C++ and Python
Co-authored-by: Dhanya Thattil <dhanya.thattil@psi.ch>
- progress looks at activated or enabled ports, so progress does not stagnate
- (eiger) disable datastreaming also for virtual servers only for 10g
- missing packets also takes care of disabled ports
