20 Commits

Author SHA1 Message Date
e91420bd16 locking in list 2020-09-18 11:23:57 +02:00
19bd39eece WIP 2020-06-16 12:47:06 +02:00
f28b41b130 WIP 2020-06-16 12:42:19 +02:00
efc247f46f WIP 2020-06-16 12:32:28 +02:00
d0baa4c7b9 WIP 2020-06-16 10:42:44 +02:00
fb5b2133f5 WIP 2020-06-15 17:13:49 +02:00
5412569e77 WIP 2020-06-15 17:10:38 +02:00
8c9341836b WIP 2020-06-15 16:26:26 +02:00
24af0ee578 WIP 2020-06-15 10:29:50 +02:00
7c2949f372 WIP 2020-06-12 17:07:58 +02:00
5a7eeb3d76 WIP 2020-06-12 16:22:31 +02:00
5aaefc8e00 fix using real detectors, moving readconfig to end (due to initialization) 2020-05-11 19:26:22 +02:00
30078d6c1f eiger: deactivate at startup, hostname activates, config file for top or master, if none, reset to hardware, no binaries 2020-05-08 18:11:15 +02:00
13c1f7c2d6 WIP 2020-05-08 16:31:26 +02:00
7d94ad51ab format slsdetectorservers .c 2020-05-05 15:30:44 +02:00
671cf45fd7 format slsdetectorservers 2020-05-05 15:23:11 +02:00
3d00eed0f0 Change SetTrimbits() and SaveAllTrimbits() to rely on top/bottom signal instead of TopAddressIsValid() for further cleanup. 2020-04-14 16:13:26 +02:00
Dhanya Thattil
98ddf154b2
Partialreadout (#47)
* eiger server, rxr: partial readout, also gui messages: up last command, down clear command

* added binaries and resolved conflict

* bugfix eiger server: interrupt subframe is bit 2 and not bit number 3

* brackets in defs
2019-08-07 09:08:58 +02:00
Dhanya Thattil
d72b6c3659 eiger server: quad, interrupt subframe, reg left and right (#45)
* eiger server: quad, interrupt subframe, reg left and right

*  eiger server: beb can fail in setting up quad, quad and gap pixels
2019-08-06 10:12:34 +02:00
89a06f099c merging refactor (replacing) 2019-04-12 10:53:09 +02:00