Commit Graph

25 Commits

Author SHA1 Message Date
67042e8315 refactorign 2025-07-02 18:11:19 +02:00
24f878a17b rois shoudl work. left to implement tests for individual rois, create multiple datasets (1 for each roi) in the virutal data file. currently virutal dataset with roi is not implemented and a warning is given instead. wonder why since the inviduviaual roi files are clipped 2025-06-20 17:20:19 +02:00
b7e17d1320 added reorder to documentation, added flag to master binary and hdf5 file
Some checks failed
CMake / Configure and build using cmake (push) Failing after 11s
2025-03-19 11:51:28 +01:00
297c3752e3 Dev/remove gotthard i (#1108)
* slsSupportLib done, at receiver rooting out in implementation

* removed from receiver and client

* removed everywhere except gui, python and client(commands.yaml and Detector.h)

* updated python

* fixed autocomplete to print what the issue is if there is one with ToString when running the autocomplete script to generate fixed.json. updated readme.md in generator folder

* formatting

* removed enums for dacs

* udpating autocomplete and generating commands

* removed gotthard from docs and release notes

* removed dac test

* bug from removing g1

* fixed virtual test for xilinx, was minor. so in this PR

* gui done

* binary in merge fix

* formatting and removing enums

* updated fixed and dump.json

* bash autocomplete

* updated doc on command line generation

* removing increments in dac enums for backward compatibility. Not required

* removed ROI from rxParameters  (only in g1), not needed to be backward compatible

* removed the phase shift option from det server staruip
2025-03-10 14:24:33 +01:00
3d21bb64c4 Dev/xilinx acq (#901)
* period and exptime(patternwaittime level 0)

* added new regsieterdefs and updated api version and fixedpattern reg

* autogenerate commands

* formatting

* minor

* wip resetflow, readout mode, transceiver mask, transceiver enable

* acquisition, but streaming done bit and busy (exposing + read chip to fifo) not known yet from fw

* programming fpga and device tree done

* most configuration done, need to connect configuretransceiver to client

* stuck at resetting transciever timed out

* minor

* fixed virtual, added chip busyto fifo, streaming busy, set/getnext framenumber

* configuretransceiver from client, added help in client

* make formatt and command generation

* tests for xilinx ctb works

* command generation

* dacs added and tested, power not done

* power added

* added temp_fpga

* binaries in

* ctrlreg is 0 to enable chip=fixed, high dac val = min val= fixed, power regulators in weird order=fixed, device tree could be loaded with dacs before adcs=fixed

* start works

* virtual server sends

* receiver works

* tests

* python function and enum generation, commands generatorn and autocomplete, formatting, tests

* tests fail at start(transceiver not aligned)

* tests passed

* all binaries compiled

* eiger binary in

* added --nomodule cehck for xilinx
2024-02-07 13:23:08 +01:00
c628ae2192 1. Ctb transceiver ro (#773)
*  transceiverenable, tsamples, romode for tranceiver and digital_transceiver

* 202 spec instr only for transceiver mode

* removed check for empty in trans readout and clean memory before reading from fifo

* ctb read fifo strobe for all after reading all channels, adding 1us after selecting channel, changing fw date

* updated 10gb transceiver enable

----
* added transceiver (tsamples, romode(transceiver, digital_transceiver), transceiverenable (mask)

* clean memory before reading from fifo (for analog and digital as well)

* read fifo then read strobe (also corresp fw) fixes number of reads (also for analg and digital)-> increases all pipelines by 1

* fixed bug in rearranging digital data in receiver

* fixed bug in streaming size of data after rearranging

* fixed bug in setbit, clearbit,and getbit

* status checks fifo before returning idle (transmitting if data in fifo if transceiver more enabled)

* soem matterhorn specifics that will need to be put into pattern in a month or two. this is temporary.

* NOTE: breaking api. rxParameters struct has transceiverenabel and tsamples given from det to receiver
2023-07-14 16:29:21 +02:00
fc24558314 formatting 2023-03-17 14:42:11 +01:00
Dhanya Thattil
532f76ed4f fix hdf5 compilation using det spec fields in header (#693)
* fix hdf5 compilation using det spec fields in header
2023-03-16 09:23:27 +01:00
Dhanya Thattil
39b1f5bbf2 Moench rewrite (#597)
* copied jungfrau server to moench and adapted

* fixed image size and num packets

* read n rows allows 16

* commneted out configure_asic_timer at server startup. To be removed later the ASIC_CTRL_REG and storage cell options

* moench:removing the decrement (which was in jf)  in read n rows to register

* removed lblsamples from gui
2022-12-15 09:16:51 +01:00
Dhanya Thattil
6bf9dbf6d3 Format (#506)
Formatted package
2022-08-05 15:39:34 +02:00
Dhanya Thattil
8ca8185d41 H5 one dataset name (#484)
* rename all datasets in hdf5 files to just 'data'

* removing the global qualifier H5

* update release notes
2022-06-09 12:35:33 +02:00
Dhanya Thattil
89aa0760c6 Hdf5fix (#483)
* hdf5 fix for string reference

* fix hdf5 compilation after namespace change
2022-06-09 11:42:32 +02:00
Dhanya Thattil
4259363169 rxr sls namespace (#457)
* rxr src files and classes (detectordata, ZmqSocket) added to sls namespace

* moving defines inside namespace

* moving defines inside namespace, added helpdacs to namespace

* added namespace to gui

* gui also updated

* removed unnecessary sls:: when already in sls namespace for slsDetectoSoftware, receverSoftware, slsDetectorGui and slsSupportlib
2022-05-18 11:48:38 +02:00
Dhanya Thattil
fcc7f7aef8 Rx roi (#428)
* roi structure expanded to have ymin and ymax

* compile with 'detector roi'

* wip

* wip, rx_roi, rx_clearroi

* wip rxroi

* rxroi wip

* wip rxroi

* merge fix

* wip

* rx_roi works, impl wip, test

* tests in, impl left

* wip, rxroi impl

* wip, rxroi impl

* wip

* setrx_Roi works, getrx_roi, wip

* rx_roi impl done

* wip, rxroi

* wip, getrx_roi rxr ports

* fix ports

* wip

* wip

* fix positions on server side

* wip

* numports wip

* wip

* jungfrau top inner interface row increment

* x, y detpos, wip

* removed eiger row indices flipping in gui (bottom flipping maintained)

* wip

* wip, jungfrau numinterfaces2

* jungfrau virtual works

* eiger, jungfrau, g2 virtual server works

* eiger positions fix, wip

* binaries in

* minor printout

* binaries in

* merge fix

* merge fix

* removing getposition

* setrxroi wip

* set upto port

* get messed, wip

* roi multi to module works, wip

* wip

* roi dont return -1

* added rxroi metadata in master file

* added rxroifromshm, not yet in detector

* rx roi in gui with box, also for gap pixels (gappixels for jungfrau mess)

* fix for segfault in gui with detaching roi box in gui

* wip

* m3 gui: slave timing modes should be discarded when squashing

* fixed m3 virtual data, and fixed counters in gui asthetics

* m3 roi works

* wip, g2

* wip

* handling g225um boards, and showing roi for gainplot as well

* udpate python functions

* fix for 1d and a2d roi written

* fixed actual roi written to file

* no virtual hdf5 when handling rx roi

* test

* minor

* binarie in
2022-05-16 12:35:06 +02:00
e1988bf088 fixes 2022-03-30 16:47:43 +02:00
c57e528447 wip, prettywriter 2022-03-30 10:43:43 +02:00
74e325edb4 removing \n in timestamp for json file 2022-03-30 09:06:09 +02:00
b9aa0f46e4 wip, hdf5 refactored 2022-03-29 13:02:57 +02:00
6cd780ae99 wip 2022-03-29 11:49:30 +02:00
f2be834d55 wip, binary file refactored for stringbuffer, hdf5 mid way, masterattributes to be de (inherited) :) 2022-03-28 17:43:58 +02:00
cbed2e88c6 wip, binary json master for other dets 2022-03-25 15:34:39 +01:00
0f02ffdc9a binary master json done, hdf5 left wip 2022-03-25 13:29:03 +01:00
90d1d0f8b8 wip, json master 2022-03-24 17:15:23 +01:00
9c1bc262e5 added geometry to master file 2022-03-16 16:09:50 +01:00
c17914e0a1 split MasterAtrributes into cpp 2022-03-16 15:49:06 +01:00