3322 Commits

Author SHA1 Message Date
2b2e50916c
dev: jf sync: stopping master gives idle (#824)
* jf sync mode master could return idle when stopped and so not all modules return the same value and must check for 'stopped or idle', Also must throw if any of the module gives an error

* added contains_only to sls::Result (#827)

* added variadic template for checking if a result contains only specified values

* fix for gcc4.8

* renamed to Result::contains_only

* updated condition in Detector.cpp

* stop on only the positions

---------

Co-authored-by: Erik Fröjdh <erik.frojdh@gmail.com>
2023-10-13 15:25:41 +02:00
dad3dc3e46
3. Dev/voltage to power (#816)
* getVoltageList, getVoltage /set, getMeasuredVoltage, getVoltageNames /set, getVoltageIndex moved to 'Power' as its misleading

* added cstdint and names slowadc,  added division to mV

* changed uV to mV in command line slow adc help. removed all python slowadcs (as it was already implemented as slowadc

---------

Co-authored-by: Erik Frojdh <erik.frojdh@gmail.com>
2023-10-02 11:11:28 +02:00
d003a6d8e0
2. Dev/add jf pedestal feature (#807) 2023-09-29 11:25:58 +02:00
88c39ba702
removing the misleading word 'Simulating' when programmig fpga (#815) 2023-09-28 16:21:31 +02:00
9834b07b47
Dev/fix port size (#805)
* port datatype changing from int to uint16_t
* throwing for -1 given for uint16_t ports
2023-09-28 09:36:39 +02:00
1873cc9310
Moench dacs defaults (#788)
* merge fix from 7.0.2: new jungfrau fw versions, incremented binary, hdf5 and json versions

* moench: changed dac names and default values to old moench values

* moench: remove interface clk polarity at start up

* moench: default speed is half speed, default values for adc offset and adc phase for different speeds (only half speed confirmed), adc vref voltage to 2.0 like G1

* moench: connected adc pipeline to client

* moench: receiver- default frames per file is 100k and discard partial frames as default

* moench binary in

* using tostring in gui for dacs

* moved frame discard policy as a parameter to be configured with a default depending on detector

* moench: 300 degrees for adc phase in full speed
2023-07-31 14:02:30 +02:00
71489b7106
2. Set row col (#779)
* set row and column
2023-07-18 15:51:22 +02:00
c628ae2192
1. Ctb transceiver ro (#773)
*  transceiverenable, tsamples, romode for tranceiver and digital_transceiver

* 202 spec instr only for transceiver mode

* removed check for empty in trans readout and clean memory before reading from fifo

* ctb read fifo strobe for all after reading all channels, adding 1us after selecting channel, changing fw date

* updated 10gb transceiver enable

----
* added transceiver (tsamples, romode(transceiver, digital_transceiver), transceiverenable (mask)

* clean memory before reading from fifo (for analog and digital as well)

* read fifo then read strobe (also corresp fw) fixes number of reads (also for analg and digital)-> increases all pipelines by 1

* fixed bug in rearranging digital data in receiver

* fixed bug in streaming size of data after rearranging

* fixed bug in setbit, clearbit,and getbit

* status checks fifo before returning idle (transmitting if data in fifo if transceiver more enabled)

* soem matterhorn specifics that will need to be put into pattern in a month or two. this is temporary.

* NOTE: breaking api. rxParameters struct has transceiverenabel and tsamples given from det to receiver
2023-07-14 16:29:21 +02:00
054e733cd5
Voltage and slow adc naming (#772)
* voltages in python 

* added voltage values in cmd line, added voltagelist in detector class

* voltage values in python

* slow adc list
2023-07-10 16:10:23 +02:00
fe4db54eb6
moench settings (#774)
* moench settings

* default value for asic ctrl reg for moench
2023-07-10 15:21:48 +02:00
5be503c1bd
moench speeds (#776)
* added other speeds and updated readoutspeedlist, test, gui
2023-07-10 15:09:51 +02:00
58cdb5bd20
added patfname command to save the file the last pttern was loaded from (#770)
* added patfname command to save the file the last pttern was loaded from
2023-06-22 09:08:48 +02:00
1a338346d5
2. Ctb fname voltage (#768)
* power and sense returning dac indices instead of int in Detector class

* power -> voltage, sense -> slowadc
2023-06-19 16:05:30 +02:00
d3d98db7e9
1. Ctb powerindices (#767)
* power and sense returning dac indices instead of int in Detector class
2023-06-19 15:19:50 +02:00
3f9ec695db
2. Patioctrl uint64 t (#766)
* when dbit list is enabled, the size of data in zmq stream is changed to only the digital bits enabled size. now fixed to also include analog size

* allowing to set 0xffffffffffffffff to pat io control. prevously was used to do a get. fixed also for pat bit mask and pat mask
2023-06-15 09:30:52 +02:00
d032f43f11 fixing tests to work and powername change bug fix from before 2023-06-14 17:19:37 +02:00
0d53f83a2f backward compatibility of alias file 2023-06-14 11:40:30 +02:00
a7dcfe4b31
Ctb sense power signal names (#759)
*  adc names

* added python functions in src

*  signal, power, sense names

* fix tests
2023-06-07 17:06:41 +02:00
b9a346a396
ctb adc names (#757)
* first draft of adc names

* fixed tests

* formatting

* added python functions in src

---------

Co-authored-by: Erik Fröjdh <erik.frojdh@gmail.com>
2023-05-31 21:07:07 +02:00
6fcb880538
Merge fix from 7.0.2 (#756)
- start acq list: mixup with master pos #743 : fix that only master starts second and not all (for start acq), typo with pos and masters list
- synced master status running when setting to slave  #747: synced master status running when setting to slave
2023-05-25 11:20:41 +02:00
65b8c9c5c1
Moench rw3 (#745)
* moench, removed chip version, filter resistor, filter cells, currentsoures, gain mode, setttings(modes), dbitphase, maxdbitphase, autocompdisable, comparatordisabletime, made acq start and stop a pulse, removed unused registers

* added parallel command

* remove gain plot for moench

* moench: updated adc invert val

* moench: update adcoffset to 0xf and adcphase to 140 degrees

* removed sync clock in moench

* updated min fw version

* removing config file in moench server
2023-05-25 11:00:23 +02:00
0a7fd0a51a
set bit and clear bit only verifies that bit (#746) 2023-05-25 10:35:17 +02:00
fb25a01db5
Automate virtual test (#714)
* using argparse for parsing command line arguments

* added command line option to specify which servers to run

---------

Co-authored-by: Erik Fröjdh <erik.frojdh@gmail.com>
2023-05-11 12:15:22 +02:00
e757e25fa1
merge fix #721 PR (sync 7.0.2.rc) to developer (#739)
* merge fix from #721 PR (sync) 7.0.2.rc -> developer
* row and column for jungfrau mixed up

* multi module jungfrau sync must do slaves first then master for start acquisition and send software trigger, and master first and then slaves for stopacquisition

* non blocking to slaves first and only then blocking/nonblocking to the master for sending software trigger(jungfrau multi mod sync)

* fixed get/set timing jungfrau when sync enabled, getsync during blocking acquire (for trigger or stop) will get stuck as it should ask the stop server

* switching between 1 and 2 interfaces did not set gui/client zmq port properly. Resulted in dummy streaming forever. fixed

* formatting, refactoring: const & for positions, multi mod M3 stop first master first

* adding missing cstdint for gcc 13

* Refactoring handle sync out, handling synchronization also for softwaretrigger for m3, for start/sync/stop for g2/g1

---------

Co-authored-by: Erik Frojdh <erik.frojdh@gmail.com>

* fixed row and col for moench 2 interfaces

* fix moench getTiming and also allow moench to handle sync

---------

Co-authored-by: Erik Frojdh <erik.frojdh@gmail.com>
2023-05-08 15:58:19 +02:00
Dhanya Thattil
b67c6dea08
ensuring no duplicate rx hostname port combo (#604)
* rx_hostname and port combo to one, or hostname to all, or a vector of hostnames and ports, ignoring none or empty, then verifying no duplicates for the host port combo including from shared memory

* extracted function for rx_hostname (#694)

* c++14 revert

* unique hostname-port combo for port, hostname, rx_tcpport (#696)

* verify unique combo for rx_port as well

* check unique hostname-port combo also when setting control port, hostname, rx_hostname and rx_tcpport

---------

Co-authored-by: Erik Fröjdh <erik.frojdh@gmail.com>
Co-authored-by: Erik Frojdh <erik.frojdh@psi.ch>
2023-03-20 12:30:12 +01:00
Dhanya Thattil
c9215a6d9b
fix old server version in 64 bits (#697)
* check server version before initial checks, catch old server version exception, get old server version as 64 bit and print it alon gwith exception
2023-03-20 10:31:27 +01:00
Dhanya Thattil
d23722a4b7
Eiger: add hardware version (#688)
* eiger: hardwareversion, fix firmware version unable to read version scenarios, check to see if febl, febr and beb have same fw version

* feb versions can be picked up only after feb initialization
2023-03-16 11:59:06 +01:00
dc5db905d4 merge from 7.0.0 2023-02-24 10:39:51 +01:00
Dhanya Thattil
48a684b95f
dev:Eiger febl febr (#601)
* eiger: get febl and febr versions in versions command, also added in python
2023-02-24 10:06:11 +01:00
Dhanya Thattil
276dc52196
dev:removed storage cells for moench (#603)
* removed storage cells for moench
* rxr: also setting moench like jungfrau in implementation of ports
2023-02-24 10:00:31 +01:00
Dhanya Thattil
ed2894dafd
python additions (#686)
* python: fixed versions when no receiver, added clearbusy, serialnumber and readoutspeedlist. commandline: modified versions to look like python versions

* python: added clkphase, fixed clkdiv, maxphase

* python added adcvpp

* gaincaps for python

---------

Co-authored-by: Erik Frojdh <erik.frojdh@gmail.com>
2023-02-23 16:29:54 +01:00
Dhanya Thattil
a74c9498e2
m3, individual chip index back in for hw 1.2, need the linux drivers for chipdac0-9 (#685) 2023-02-23 09:13:31 +01:00
a098bc4674 fixes for tests for m3 2023-02-22 14:34:01 +01:00
Dhanya Thattil
6faa4c821f
udp_srcip auto to detector ip (#683)
* udp_srcip now points to detectorip for 'auto' argument. and not allowed for G1
2023-02-22 11:09:52 +01:00
Dhanya Thattil
da291d535e
fix ctb test, non blocking will not return for 1g (#684)
* fix ctb test, non blocking will not return for 1g
2023-02-22 11:09:18 +01:00
Dhanya Thattil
b200a2efc1
Fix jf softwre trigger and tests with real jungfrau detector (#673)
* jungfrau: software triggers do not work, fixed

* eiger test: get highvoltage must be read twice to get the real voltage
2023-02-20 15:22:46 +01:00
Dhanya Thattil
fe281bd1b1
Fix stop rx stuck (#669)
stop should really stop even if receiver had crashed, so check rx status after sending stop; also ensuring restream  in acquire happens only if thers a callback
2023-02-20 15:21:22 +01:00
cb8e4365e3 formatting 2023-02-14 15:08:31 +01:00
Erik Fröjdh
0251aa9e63
fixed linking issue in arping and shm test (#659)
Co-authored-by: Erik Frojdh <erik.frojdh@psi.ch>
2023-02-14 14:49:00 +01:00
Dhanya Thattil
572332f870
fix test for eiger half module for gap pixels (#658) 2023-02-14 09:22:32 +01:00
d90bf6c7df formatting 2023-02-13 11:36:41 +01:00
Dhanya Thattil
5c8c3ae3f3
fix to access to shared memory that doesnt exist (#638)
* fix to access to shared memory that doesnt exist

* fix for freeing shm and then setting hostname from API

* exception error message moved to private function

* refactoring to avoid allocating intermediate string
2023-02-13 11:29:54 +01:00
4ee4d66977
Jf zeromq display (#644)
* modified ZmqSocket to expose the SO_RCVBUF and SO_SENDBUF parameters. Modified DataStreamer.cpp to change the SENDBUF to 1MB when HWL is <10. Modified Datastreamer.cpp so that when HWL is changed, socket is unbind/rebind. Added rebind to ZmqSocket.cpp.
Changed slot UpdatePlot() in qdrawplot.h from privat tto public, added plot->UpdatePlot() after every axis range change, so the plots are updated immediatly and not at the next image.
Added onlinedisp_zmq program which connects to the receiver ZMQ port and show images and histos. Compiled against  ROOT 6.22/02. Added examples files.

* added setbuffer size also for gui, moved hardcoded values to a macro, removed unnecessary return of ok or success, added actual zmq exception message to could not create sockets error

* zmq: changing buffer size done within hwm

---------

Co-authored-by: mozzanica <l_mozzanica@mpc2012.psi.ch>
Co-authored-by: Dhanya Thattil <dhanya.thattil@psi.ch>
2023-02-09 17:24:28 +01:00
Dhanya Thattil
e14f6981a0
Fix tests (#647)
* fixes tests
2023-02-09 15:57:05 +01:00
Dhanya Thattil
ebb6f53b21
Fix rx arping socket bind (#646)
* first tries with a process intead of thread for rx_arping

* Moving delete pointer of udp socket to stopReciever,so rx_arping can only be set when udp socket is closed

* refactoring and formatting

* unused variable processId

* ignore sigchild to prevent zombie from child processes being killed
2023-02-03 17:18:09 +01:00
e172df79f3 format 2023-02-03 11:23:19 +01:00
Dhanya Thattil
9ba907f9f7
added none or 0 to unset bad channels (#632)
* added none or 0 to unset bad channels

* free function split to get int array from string of arguments for badchannels

* missed a file

* allowing list for badchannels in command line

* added badchannels in python

* added size check

* more comments in Detector.h and added more tests for facny command line badchannels

* removeDuplicates accept any container, added tests

* corner cases: 1:5,6,7 or 5,6,7 or just 1:5

Co-authored-by: Erik Frojdh <erik.frojdh@gmail.com>
2023-01-27 09:59:31 +01:00
0b17318f10 formatting 2023-01-24 10:37:52 +01:00
Dhanya Thattil
c5b621b684
intialize pattern addresses with default, else they are created with value 0 and overwrite the default in server (#628) 2023-01-23 10:59:18 +01:00
Dhanya Thattil
946e6aa817
badchannel segfault for multi module (#620)
* badchannels segfaults when there are no badchannels for next modules, fixed

* added example badchannels

* refactoring casting
2023-01-20 17:39:25 +01:00