Commit Graph

12 Commits

Author SHA1 Message Date
maliakal_d 5ec5d46c48 Dev/ctb separate dac and power (#1420)
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* not allowing power names for dac names to prevent duplicate names

* wip

* v_abcd commands should be removed to prevent unintentional usage and throw with a suggestion command for dac and power

* binary in

* dacs with power dac names should work and do not take in dac units to avoid ambiguity, test with 0 value for power dacs should fail, to do: implement power commands

* wip: power in client, tests, and fixed server interfaces and ctb implementation, not tested

* wip. client and xilinx todo

* wip: ctb power works, tests left

* fixed some tests

* added vchip check

* python cmds still left. wip

* fixed xilinx. python left

* wip

* wip. xilinx

* fixed powerchip for ctb

* power all returns all

* configtransceiver is removed

* wip python

* wip

* wip

* wip

* wip

* wip

* wip

* wip xilinx

* wip

* wip

* wip

* pybindings

* fix getdacindex and getdacname for normal detectors to throw if random index that doesnt fit to the detector

* wip

* fixed tests

* fixes for python api

* wip

* python: moved powerlist to Ctb

* fixed tests to work for powelist in Ctb

* moved signallist, adclist, slowadc, slowadclist to Ctb

* throw approperiate error when no modules added for powers

* added dac test

* fix dac default names and test for dacs

* ctb dacs, yet to do othe rdacs

* dacs should work now even in tests

* run all tests

* DetectorPowers->NamedPowers in ctb

* comments

* removed unnecessary test code

* removed hard coded dac names in python NamedDacs and NamedPowers

* minor

* minor

* fixed error messages

* changed power to  be able to set DAC directly, using enable and disable methods with enabled to get
2026-04-15 10:33:01 +02:00
maliakal_d 3dd07bf2be Dev/define cmd (#1312)
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Build on RHEL8 / build (push) Successful in 4m44s
* basic ctb config api for register and bit names

* tests for define and definelist pass. yet to implement using them for reg, setbit, clearbit and getbit

* improved autocomplete for getbit,setbit, clearbit

* validate autocomplete

* definelist has no put

* updating help

* converting char array+int in runtimeerror compiles but throws at runtime.Fixed.Tested for it. Also check if string or int before using getregisterdefinitonbyvalue to see if it threw to call the other function. because both of it can throw and we should differentiate the issues for both

* removed std::vector<std::pair<string,int> to std::map<string, int> for defiitions list

* Dev/define cmd tie bit to reg (#1328)

* strong type

* moved everythign to bit_utils class

* pybindings

* added tests for python

* removed duplicates

* removed bit names in reg

* changed BitPosition to BitAddress

* Using define reg/bit from python (#1344)

* define_bit, define_addr in python. 
* setBit/clearBit takes int or addr

* added example using bits

* split define into 2 commands define_reg and define_bit, definelist into 2: definelist_reg and definelist_bit

* allow string for register and bit names in c++ api

* refactor from github comments

* naming refactoring (getRegisterDefnition to retunr name and address specifically

* added marker for 8 cmd tests connected to define, changed macro to static constexpr

* changed bitPosition from int to uint32_t

* got rid of setbitposition and setaddress, instead overloaded constructor to take in strings so that the conversion from string to bit address members, takes place within the class for easy maintainance in case type changes

* Removing implicit conversions:
RegisterAddresss and RegisterValue: Removed the implicit conversions.
RegisterAddress: Changed member name from address_ to value_ and method as well to value().
RegisterValue: Also added | operator to be able to concatenate with uint32_t. Same in python bindings (but could not find the tests to modify

* Allowed concatenation with other RegisterValue, made them all constexpr

* fix a ctbConfig test

* Maponstack works with integration tests, but need unit tests

* tests on mapstack

* fixed ctb tests and FixedString being initialized with gibberish

* removing parsing from string inside the class RegisterAddress, BitAddress and RegisterValue

* updated python bindings

* fixed bit utils test

* renaming getRegisterDefintiionAddress/Name=>getRegisterAddress/Name and similary for getBitDefinitionAddress/Name

* updated python bindings

* fix tests (format)

* a few python tests added and python bindings corrected

* replaceing str with __str__ for bit.cpp

* repr reimplemented for bit.cpp

* removed make with registerAddress etc

* starting server for tests per session and nor module

* killprocess throws if no process found-> github runs fails, changed to pkill and not throw

* clean shm shouldnt raise, in ci binary not found

* ignoring these tests for CI, which fail on CI because simulators are not generated in CI. This is in another PR, where it should work

---------

Co-authored-by: Erik Fröjdh <erik.frojdh@gmail.com>
Co-authored-by: froejdh_e <erik.frojdh@psi.ch>
2026-01-05 15:10:46 +01:00
maliakal_d dad3dc3e46 3. Dev/voltage to power (#816)
* getVoltageList, getVoltage /set, getMeasuredVoltage, getVoltageNames /set, getVoltageIndex moved to 'Power' as its misleading

* added cstdint and names slowadc,  added division to mV

* changed uV to mV in command line slow adc help. removed all python slowadcs (as it was already implemented as slowadc

---------

Co-authored-by: Erik Frojdh <erik.frojdh@gmail.com>
2023-10-02 11:11:28 +02:00
maliakal_d 054e733cd5 Voltage and slow adc naming (#772)
* voltages in python 

* added voltage values in cmd line, added voltagelist in detector class

* voltage values in python

* slow adc list
2023-07-10 16:10:23 +02:00
maliakal_d 1a338346d5 2. Ctb fname voltage (#768)
* power and sense returning dac indices instead of int in Detector class

* power -> voltage, sense -> slowadc
2023-06-19 16:05:30 +02:00
maliakal_d d3d98db7e9 1. Ctb powerindices (#767)
* power and sense returning dac indices instead of int in Detector class
2023-06-19 15:19:50 +02:00
maliakal_d d032f43f11 fixing tests to work and powername change bug fix from before 2023-06-14 17:19:37 +02:00
maliakal_d 0d53f83a2f backward compatibility of alias file 2023-06-14 11:40:30 +02:00
maliakal_d a7dcfe4b31 Ctb sense power signal names (#759)
*  adc names

* added python functions in src

*  signal, power, sense names

* fix tests
2023-06-07 17:06:41 +02:00
maliakal_d b9a346a396 ctb adc names (#757)
* first draft of adc names

* fixed tests

* formatting

* added python functions in src

---------

Co-authored-by: Erik Fröjdh <erik.frojdh@gmail.com>
2023-05-31 21:07:07 +02:00
Dhanya Thattil 6bf9dbf6d3 Format (#506)
Formatted package
2022-08-05 15:39:34 +02:00
Erik Fröjdh 1ff35edb99 Setting dac names for CTB (C++ and Python) (#413)
# Setting DAC names for CTB
* Introduced new shared memory for CTB only
* Prepared for additional functionality 
* Works from C++ and Python

Co-authored-by: Dhanya Thattil <dhanya.thattil@psi.ch>
2022-03-28 14:27:47 +02:00