Erik Fröjdh
10b315c2bd
Mythen3 improved synchronization ( #231 )
...
Disabling scans for multi module Mythen3, since there is no feedback of the detectors being ready
startDetector first starts the slaves then the master
acquire firs calls startDetector for the slaves then acquire on the master
getMaster to read back from hardware which one is master
2021-02-08 13:28:37 +01:00
Dhanya Thattil
f9f50f1d84
M3settings ( #228 )
...
* added temp m3 settings files
* renames settings noise to trim
* get threshold for M3
* some changes to compile on RH7 and in the server to load the default chip status register at startup
* Updated mythen3DeectorServer_developer executable with correct initialization at startup
Co-authored-by: Erik Frojdh <erik.frojdh@gmail.com>
Co-authored-by: Anna Bergamaschi <anna.bergamaschi@psi.ch>
2021-01-14 12:34:13 +01:00
Dhanya Thattil
a62e068a9a
M3defaultpattern ( #227 )
...
* default pattern for m3 and moench including Python bindings
Co-authored-by: Erik Frojdh <erik.frojdh@gmail.com>
2020-12-09 13:28:39 +01:00
1ce56764fa
binaries in
2020-11-30 13:59:55 +01:00
e382df21b9
updated binaries, links in serverBin and deleted v5.0.0 binaries
2020-11-27 14:26:15 +01:00
Dhanya Thattil
e63fa1d7c2
Setting pattern from memory ( #218 )
...
* ToString accepts c-style arrays
* added patternParameters to python
* fixed patwait time bug in validation
* moved load from file function to patterParameters
* server using patternparamters structure to get pattern
Co-authored-by: Erik Frojdh <erik.frojdh@gmail.com>
2020-11-24 20:32:07 +01:00
10fa57ebb9
binaries updated to reflected developer branch
2020-11-19 16:44:40 +01:00
8be579ea53
binaries name changed
2020-11-17 18:41:18 +01:00
73d582744e
updated binaries for 5.0.0
2020-11-17 16:49:03 +01:00
980d76a15a
binaries in
2020-11-17 11:03:16 +01:00
121450b8cc
binaries in
2020-11-17 11:02:23 +01:00
Dhanya Thattil
a6d696a0f8
Nextframenumber ( #215 )
2020-11-16 17:26:12 +01:00
Dhanya Thattil
4c4e2ccb6b
Defaultdacs ( #214 )
2020-11-13 08:31:02 +01:00
98fce317a8
binaries in
2020-11-02 16:39:06 +01:00
f6189072bc
binaries in
2020-10-27 18:17:37 +01:00
Dhanya Thattil
47018b61cd
M3readout ( #209 )
...
* m3: readout command
2020-10-26 16:13:48 +01:00
b31f8a5ca6
binary in
2020-10-20 12:05:18 +02:00
a86d70235c
binaries in
2020-10-16 15:03:56 +02:00
fddc93ba8d
binaries in
2020-10-15 09:28:41 +02:00
12abf3e58b
binary in
2020-10-09 17:56:36 +02:00
a310ab9bfa
updated all servers
2020-10-09 16:59:46 +02:00
e0e2c2efba
updated binaries
2020-10-08 15:55:24 +02:00
33d85dbfc0
all servers compiled
2020-10-08 15:45:29 +02:00
5c0dff29ed
binaries in
2020-10-07 12:27:35 +02:00
c2d9532a69
updated versionign server color minor
2020-10-05 09:56:47 +02:00
7855005590
updated 5.0.0-rc2 in binaries
2020-10-05 09:53:13 +02:00
b2f5208745
binaries in
2020-10-02 11:19:19 +02:00
Dhanya Thattil
3f19f29c9e
G2ContTrigger ( #188 )
...
* g2: setting #frames to 1 and period to 0 for cont trigger, extra frame reg is set to #frames for cont auto and #trigger for cont trigger
2020-09-24 11:59:11 +02:00
5214c0f1a4
binaries in
2020-09-10 18:43:26 +02:00
88fe306902
binaries in
2020-09-10 16:23:29 +02:00
80b053eb10
binaries resolved, merge conflict from developer
2020-09-10 10:19:34 +02:00
Dhanya Thattil
3cd4f3897b
M3: software trigger ( #175 )
2020-09-10 10:15:45 +02:00
52303daffd
binaries in
2020-09-09 16:44:23 +02:00
a9d1a78662
m3:smp_clk (timing rxr) changed back to clk div 5
2020-09-09 15:55:13 +02:00
3cf2160a2d
binaries in
2020-09-09 15:25:48 +02:00
b33fdf4462
merge conflict fixed and merged with developer
2020-09-09 12:31:36 +02:00
6c8443f09e
binaries in
2020-09-09 12:14:38 +02:00
97687f0f6d
binary in
2020-09-08 17:33:06 +02:00
87bad38f80
binary in
2020-09-08 15:46:32 +02:00
e1e04ee755
binaries in
2020-09-08 15:18:07 +02:00
aecde086a0
binaries in
2020-09-08 12:16:41 +02:00
f26d8e514b
merged with g2continuous
2020-09-08 08:46:37 +02:00
0b9ff70244
binaries in
2020-09-08 08:25:24 +02:00
891b8dbd2c
mythen3: wrong hardware version number, so it didnt reboot after programfpga
2020-09-03 17:04:58 +02:00
00978a52c8
added smp_clk, changed rdo vco freq from 1.25GHz to 1GHz, changed rdo clock dividers
2020-09-01 12:06:39 +02:00
7ea86dec43
m3 binaries in
2020-08-18 15:28:30 +02:00
27b2a607c8
binaries in
2020-08-10 12:05:37 +02:00
bbf8ab4b88
binary in
2020-08-05 09:49:13 +02:00
321ed13659
merge from developer
2020-08-04 17:43:38 +02:00
f6172f9b9e
binary in
2020-08-04 17:36:49 +02:00
