4 Commits

Author	SHA1	Message	Date
Dhanya Thattil	1d4a5d6d29	dev: jungfrau HW 1.0: adc output clock phase to 120 (#952) ... * jungfrau: change adc output clock phase from 180 to 120 for v1.0 boards for reliable readout of adc #2 * versioning * formatting	2024-08-22 15:45:41 +02:00
Dhanya Thattil	4de7bb51ed	updated all .h files with license notice and copyright notice	2021-10-14 18:10:56 +02:00
Dhanya Thattil	671cf45fd7	format slsdetectorservers	2020-05-05 15:23:11 +02:00
Dhanya Thattil	0d35b966ff	Separate headers (#57) ... * WIP, ctb * WIP, eiger * WIP, gotthard * WIP, jungfrau * WIP, gotthard2 * WIP, mythen3 * WIP, moench * fixed gotthard apiversioning mismatch with gotthard2	2019-08-30 11:17:37 +02:00