11 Commits

Author	SHA1	Message	Date
Erik Frojdh	959fd562d3	clang-format	2020-05-04 16:30:00 +02:00
maliakal_d	7c7f7e8c70	testing WIP	2020-04-03 16:20:05 +02:00
maliakal_d	6a6af528ef	testing WIP	2020-03-30 13:25:39 +02:00
Dhanya Thattil	4813b5567a	Minimal shared memory for receiver	2020-03-19 07:01:32 +01:00
Dhanya Thattil	11e7737a2f	gotthard2: timingsource and currentsource features, (timing source external yet to be implemented in fpga to test (#80)	2020-02-28 12:45:02 +01:00
maliakal_d	ec76590f28	Merge branch 'developer' into bursts	2020-02-26 09:29:18 +01:00
maliakal_d	2fcb2bff75	dac tests	2020-02-26 09:29:06 +01:00
maliakal_d	6a0a931e3e	gotthard2: bursts and burst period, written to same register as triggers and delay (kept in server as variables) and set if conditions meet. bursts and burst period only in auto timing and burst mode. Also updating theses registers when switching between timing modes or burst modes	2020-02-25 15:45:40 +01:00
maliakal_d	ac3230c656	gotthard2 testing	2020-01-29 14:34:23 +01:00
maliakal_d	69897d4c78	WIP testing	2020-01-27 13:56:44 +01:00
maliakal_d	1dea112742	adding gotthard2 tests	2020-01-22 11:35:29 +01:00