* period and exptime(patternwaittime level 0)
* added new regsieterdefs and updated api version and fixedpattern reg
* autogenerate commands
* formatting
* minor
* wip resetflow, readout mode, transceiver mask, transceiver enable
* acquisition, but streaming done bit and busy (exposing + read chip to fifo) not known yet from fw
* programming fpga and device tree done
* most configuration done, need to connect configuretransceiver to client
* stuck at resetting transciever timed out
* minor
* fixed virtual, added chip busyto fifo, streaming busy, set/getnext framenumber
* configuretransceiver from client, added help in client
* make formatt and command generation
* tests for xilinx ctb works
* command generation
* dacs added and tested, power not done
* power added
* added temp_fpga
* binaries in
* ctrlreg is 0 to enable chip=fixed, high dac val = min val= fixed, power regulators in weird order=fixed, device tree could be loaded with dacs before adcs=fixed
* start works
* virtual server sends
* receiver works
* tests
* python function and enum generation, commands generatorn and autocomplete, formatting, tests
* tests fail at start(transceiver not aligned)
* tests passed
* all binaries compiled
* eiger binary in
* added --nomodule cehck for xilinx
Firmware updated. spi moved to firmware. In Software, configuring, then a pulse to start, wait for done bit and convert the values read from a regiter.
* eiger: moved rate correction outside, fixed threshold energy bug in client (binaries not updated yet)
* removed dr and deadtiem from shm
* help for rx_status and status to point them to rx_Start, rx_stop, start and stop
* moved progress to receiver
* removed currentsettings from eiger shm
* updated server binaries, and client api
* moench and ctb virtual servers compile fix
* gui: moved acquire to a concurrent qt thread so it doesnt block updateplot
