* voltage regulators only looks at dac and not at ctrl_reg
* xilinx: change dac max to 2048, setting dac ist not inverse conversion from dac to voltage anymore, but setting power is inverse, also there is max and min to power, a different min for vio and this is checked at funcs interface, not printign or converting to mv in dac for power regulators (as its conversion max and min are different)
* Use links for dacs/adc and adapt power rglt thresholds
* Remove wait for transceiver reset
* adc and dac device not used anymore and hence removed
* udp restucturing: arm has to be multiple of 16 and no byteswap in udp_gen, option to compile locally in arm architecture, memsize of the second udp memory has to be limited
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Co-authored-by: Martin Brückner <martin.brueckner@psi.ch>
* period and exptime(patternwaittime level 0)
* added new regsieterdefs and updated api version and fixedpattern reg
* autogenerate commands
* formatting
* minor
* wip resetflow, readout mode, transceiver mask, transceiver enable
* acquisition, but streaming done bit and busy (exposing + read chip to fifo) not known yet from fw
* programming fpga and device tree done
* most configuration done, need to connect configuretransceiver to client
* stuck at resetting transciever timed out
* minor
* fixed virtual, added chip busyto fifo, streaming busy, set/getnext framenumber
* configuretransceiver from client, added help in client
* make formatt and command generation
* tests for xilinx ctb works
* command generation
* dacs added and tested, power not done
* power added
* added temp_fpga
* binaries in
* ctrlreg is 0 to enable chip=fixed, high dac val = min val= fixed, power regulators in weird order=fixed, device tree could be loaded with dacs before adcs=fixed
* start works
* virtual server sends
* receiver works
* tests
* python function and enum generation, commands generatorn and autocomplete, formatting, tests
* tests fail at start(transceiver not aligned)
* tests passed
* all binaries compiled
* eiger binary in
* added --nomodule cehck for xilinx
* WIP
* WIP virtual delays, imagetest for saturation
* WIP, vertical and horizontal
* WIP
* gap pixels work, fixed 32 bit data out (10gbe=0) for virtual servers
* quad works (also in virtual), handling gappixels and quad
* jungfrau gapppixels work
* jungfrau: done
* complete image or missing packets given in json header and gui
* eiger virtual 4 bit mode bug fix
* working version of zmq add json header, except printout
* printout bug
* fix for json para
* to map WIP
* map done
* map print , mapwith result left
* json result works, testing added
* updated server binaries
* compiling on rhels7, variable size char array iniitalization
* zmqsocket parsing didnt need Document
* const to map, json para is strings not map
* json add header: mapping cleaner without insert make_pair
