353 Commits

Author	SHA1	Message	Date
maliakal_d	c1d28e47d4	wip	2021-09-02 15:52:52 +02:00
maliakal_d	4daac1a06a	wip	2021-09-02 15:46:31 +02:00
maliakal_d	e0f686231a	wip	2021-09-02 15:37:28 +02:00
maliakal_d	a51deda2a4	moduleid for eiger m3 and g2, but set only for g2	2021-09-01 17:06:34 +02:00
maliakal_d	25d03f949e	partialread changed to readnrows	2021-08-31 16:46:49 +02:00
maliakal_d	861c81d57a	wip	2021-08-31 14:42:36 +02:00
maliakal_d	1d989637e9	udp_firstdst for jungfrau	2021-08-25 14:27:06 +02:00
maliakal_d	ab59f7db7b	added udp_numdst	2021-08-19 15:50:02 +02:00
maliakal_d	f8d8fcf48a	wipg	2021-08-18 19:05:05 +02:00
maliakal_d	c4c16ad9c0	wip	2021-08-17 14:05:59 +02:00
maliakal_d	f72f678d45	Merge branch 'developer' into roundrobin	2021-08-17 11:06:13 +02:00
maliakal_d	5790e4961b	wip	2021-08-13 17:10:46 +02:00
maliakal_d	62d697e91f	readnlines->partialread, better debugging for TCP socket interface bug	2021-08-13 12:34:50 +02:00
maliakal_d	ec01f98c26	wip	2021-08-12 17:37:55 +02:00
maliakal_d	200df88dcf	module id instead of serial number	2021-08-12 11:16:10 +02:00
maliakal_d	6f54402aba	g2: setting serialnumber allowed	2021-08-11 18:50:49 +02:00
maliakal_d	9a777b13bb	g2: dbitpipeline	2021-08-11 18:01:28 +02:00
maliakal_d	fce35e35a1	wip	2021-08-10 17:26:26 +02:00
maliakal_d	dd3f2db3c5	binaries in, merge fix	2021-08-06 16:18:28 +02:00
maliakal_d	4986a5e61a	Merge branch 'j13flippeddatax' into j7filter	2021-08-06 16:16:46 +02:00
maliakal_d	e62fc1907f	binaries in, merge fix	2021-08-06 16:16:25 +02:00
maliakal_d	cc3aede979	merge fix	2021-08-06 16:11:58 +02:00
maliakal_d	2c53a134cd	updated i3gbe to lll	2021-08-06 16:08:07 +02:00
maliakal_d	2934ccbf2c	filter cell (only chipv1.1)	2021-08-06 14:42:41 +02:00
maliakal_d	86126c7e27	filter resistor in	2021-08-05 16:56:53 +02:00
maliakal_d	619f3b71c1	flippeddataoverxaxis changed to flipRows	2021-08-05 14:44:25 +02:00
maliakal_d	c5d6dd0dd4	flippeddatax for jungfrau server	2021-08-05 12:39:04 +02:00
maliakal_d	9c4ecf0506	jungfrau: comp disable time	2021-08-03 13:12:58 +02:00
maliakal_d	9ed3a294ce	jungfrau: gainmode	2021-08-02 12:44:57 +02:00
maliakal_d	9c03e83ef1	reset default dacs	2021-07-29 16:34:38 +02:00
maliakal_d	de7f4489af	defaultdac upto detector side, settings is undefined when none given	2021-07-28 20:11:58 +02:00
maliakal_d	cb293f9945	j: 1. chipversion	2021-07-22 16:48:35 +02:00
maliakal_d	05b7e0ef42	conflict merge fix	2021-07-22 11:53:00 +02:00
maliakal_d	da996314e7	merge conflict	2021-07-22 11:15:57 +02:00
maliakal_d	ec7ba7c508	wip to change to enum for portposition	2021-07-20 16:05:08 +02:00
maliakal_d	e02493d4e4	veotalg for g2	2021-07-20 14:57:31 +02:00
maliakal_d	af16ad4040	vetoalg: wip	2021-07-20 12:58:05 +02:00
maliakal_d	780d4bfe0a	gotthard2: vetostream (detector: only 3gbe, 10gbe via numudpinterfaces)	2021-07-15 16:21:17 +02:00
maliakal_d	fdf6632356	wip	2021-07-05 15:20:34 +02:00
maliakal_d	cbdb05a3a8	wip	2021-07-01 15:11:22 +02:00
maliakal_d	18fe63f594	wip	2021-06-28 13:32:44 +02:00
maliakal_d	8b22b5dbe7	wip	2021-06-25 17:13:40 +02:00
maliakal_d	1b525abfa1	wip	2021-06-25 17:11:36 +02:00
maliakal_d	61c5018a46	wip	2021-06-23 10:28:14 +02:00
maliakal_d	755738a42e	wip	2021-06-22 20:50:50 +02:00
maliakal_d	b11f6c56e7	getmaster through stop server, allowing stopacq to first go to slave for eiger, eiger stop to first check reg value to send complete frames before calling stop	2021-06-15 12:59:54 +02:00
maliakal_d	0afe093afc	wip	2021-06-04 12:30:59 +02:00
Erik Frojdh	085ea3aee7	dont add detector id for .trim	2021-04-27 08:28:05 +02:00
Erik Frojdh	be5fee8126	M3: fixed gain bits with negative polarity	2021-04-12 16:44:47 +02:00
Erik Frojdh	01c785271f	WIP	2021-03-31 16:26:36 +02:00