7 Commits

Include renames

Author	SHA1	Message	Date
3 people	ed6024c026	Use svg images in docs, fix typos (#1487) ... * replaced png images with svg * fixed docs typos * fix filename * fix image references, filename in index * fixed drawio svg export, upd drawio plots --------- Co-authored-by: Dhanya Thattil <dhanya.thattil@psi.ch> Co-authored-by: Erik Fröjdh <erik.frojdh@gmail.com>	2026-08-14 14:06:37 +02:00
3 people	2d8f93a426	ctb: add patternstart command, xilinx: fix frequency (#1307) ... * add patternstart command for CTB, block end of execution udp packets if pattern was started by patternstart command * update docs * Dhanya's comments * more Dhanya comments * refactored * fixed tests for startpatttern, also clkfrequency not properly used in server * xilinx: fixed setfrequency, tick clock (with sync clock), clkfrequency set from getfrequency to get the exact value * xilinx freq in kHz, updated default values and prints --------- Co-authored-by: Martin Mueller <martin.mueller@psi.ch> Co-authored-by: Dhanya Thattil <dhanya.thattil@psi.ch>	2025-09-23 12:13:46 +02:00
3 people	e7a91d38f2	Pattern unification & Matterhorn Changes (#1303) ... * update ctb regDefs, included fill level of adc, transceiver and DBit fifos, added enable registers for cont. readout * fix fifo fill level range bug * updated ctb RegDefs, increased size of fifo fill level register * added register to read the firmware git hash * ctb: added altchip_id read register * start with unification of pattern machinery for xctb, ctb, mythen * udate addrs for d-server internal matterhorn startup * update xctb reg defs * move pattern loopdef start * added zero trimbits to matterhorn config * Revert "added zero trimbits to matterhorn config" This reverts commit 7c347badd5. * added adjustable clocks on Xilinx-CTB * added support for fractional dividers of runclk * XCTB: make frequencies adjustable from python gui * update docs * added support for patternstart command to XCTB * XCTB: map pattern_ram directly into memory, removed rw strobe * refactor Mythen pattern control addresses * test altera ctb with common addresses, removed ifdefs * change ordering of regdefs * updated python help for dbitclk, adcclk and runclk (khz) * xilinx: moved the wait for firmware to measure the actual frequency to the server side and removed it in the pyctbgui side * will not be anymore in developer branch * make format (exception RegisterDefs.h), rewrite XILINX PLL to have less consstants in the code * bug: mixing && for & --------- Co-authored-by: Martin Mueller <martin.mueller@psi.ch> Co-authored-by: Dhanya Thattil <dhanya.thattil@psi.ch>	2025-09-17 17:28:17 +02:00
muelle_m1	0b3cd499a8	Dhanya's comments	2025-04-02 10:18:57 +02:00
muelle_m1	46152d2419	added mythen3 pattern word table	2025-03-28 09:35:25 +01:00
muelle_m1	dc85a48864	update xilinxCtb pattern bit mapping	2025-03-27 18:03:02 +01:00
muelle_m1	dc8a34592a	started pattern docu	2025-03-27 17:03:36 +01:00