Dhanya Thattil
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5ca3a1b685
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gotthard2 and mythen3: programming fpga, reboot; jungfrau, ctb: modified programming (#74)
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2020-01-30 19:52:35 -08:00 |
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1797d39216
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updated mythen3 to configure phase, freq, delay left, period left, actual time, measurement time, framesfrom start and othe register mappings
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2019-11-06 18:58:22 +01:00 |
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Marie Andrä
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5f94b5c246
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Dac (#67)
* dac WIP
* dacs WIP
* DACs are working with names
* namechanges of vrfsh->vshaper, vrfshnpol->vshaperneg
* pattern for MY3, configure MAC for MY3
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2019-10-07 12:13:25 +02:00 |
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Marie Andrä
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6e6fcec698
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MY3.0:read and write Registers, frames, cycles, delay (#64)
* MY3.0:read and write Registers, frames, cycles, delay
* write pattern seems to work
* done all corrections. added default clks: run_clk=125MHz, tick_clk=20MHz (fix), sampling_clk=80MHz (from Carlos)
* clk check for aquistition time
* clk check for aquistition time
* Update slsDetectorServer_defs.h
* Update slsDetectorFunctionList.c
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2019-09-30 14:36:33 +02:00 |
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Erik Frojdh
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27d223d199
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testing
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2019-09-19 12:12:25 +02:00 |
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Dhanya Thattil
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0d35b966ff
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Separate headers (#57)
* WIP, ctb
* WIP, eiger
* WIP, gotthard
* WIP, jungfrau
* WIP, gotthard2
* WIP, mythen3
* WIP, moench
* fixed gotthard apiversioning mismatch with gotthard2
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2019-08-30 11:17:37 +02:00 |
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4b7ab98135
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initial functions for mythen3
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2019-08-22 15:55:27 +02:00 |
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72362b0334
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first version of mythen3
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2019-08-22 12:34:06 +02:00 |
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