Dhanya Maliakal
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af079f3168
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posisibility to read adnd write registers in the front end board for eiger
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2017-08-10 14:49:02 +02:00 |
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Dhanya Maliakal
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111856ed7b
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hv should work now
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2017-01-06 15:16:05 +01:00 |
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Dhanya Maliakal
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0fdbac981e
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should work for serial comm hv for 9m
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2017-01-05 12:58:49 +01:00 |
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Dhanya Maliakal
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b1a3a224ff
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implemented high voltage for normal modules
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2016-11-11 14:43:18 +01:00 |
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Dhanya Maliakal
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81d96a047d
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slsDetector/slsDetectorCommand.cpp
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2016-10-20 07:31:53 +02:00 |
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Dhanya Maliakal
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03cdda99ae
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fixed bug in temp front fpga
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2016-10-07 15:54:46 +02:00 |
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Dhanya Maliakal
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28f96f4b51
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included a febl and febr temp read
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2016-10-07 15:44:13 +02:00 |
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Dhanya Maliakal
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a4bb3fe4dd
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merged with 2.1.1-rc inclding deactivate detectr and receiver
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2016-10-04 14:06:47 +02:00 |
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Dhanya Maliakal
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0979d04693
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works for deactivated server and receiver
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2016-10-04 07:35:52 +02:00 |
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Dhanya Maliakal
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5f4a4b0d90
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maybe fixed 16 bit rate corr eiger
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2016-09-23 17:15:16 +02:00 |
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Dhanya Maliakal
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d904f7b32e
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adding 16 bit rate correction in eiger
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2016-09-23 14:28:20 +02:00 |
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Dhanya Maliakal
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9c9d946d70
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fixed bug subexptime >=2.2 was set to weird value, was a int to int64_t error in server
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2016-07-18 13:37:13 +02:00 |
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Dhanya Maliakal
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3c4b0c24c8
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rate correction for eiger implemented
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2016-02-10 11:24:49 +01:00 |
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Dhanya Maliakal
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9067da5e88
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rate correction for eiger implemented
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2016-02-10 11:22:59 +01:00 |
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Dhanya Maliakal
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f0c4a4a7e4
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almost done
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2016-02-08 15:20:19 +01:00 |
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Dhanya Maliakal
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cf3e736d7e
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fixed bug that still reads hostname and expects a 0XX format, also prints revision number in decimal and not hex
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2016-02-08 11:25:10 +01:00 |
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Dhanya Maliakal
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23058987a4
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mid way, had to change to fix bug
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2016-02-08 11:11:36 +01:00 |
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Dhanya Maliakal
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8ae1e812e6
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pulse chip fixed
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2015-11-20 16:41:27 +01:00 |
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Dhanya Maliakal
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c097dfc8b3
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two acquires at the same tiem should not be possile. using shared memory to set flag, made all connect use the standard connectControl etc
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2015-11-20 16:28:48 +01:00 |
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Dhanya Maliakal
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a1bd54b16b
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pulsing in client and server
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2015-11-19 17:43:46 +01:00 |
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Dhanya Maliakal
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8b0895add0
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reset counter bit in eiger detector partially or completely
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2015-11-17 16:39:36 +01:00 |
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Dhanya Maliakal
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584b9e6036
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added gain and offsets to the shared memory, that are sent along with sls_detector_module, only for eiger
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2015-09-04 15:54:12 +02:00 |
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Dhanya Maliakal
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cae286941a
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added subframe exposure time settable
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2015-09-03 15:16:48 +02:00 |
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Dhanya Maliakal
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302d9ca0ed
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added the code for toggle bit to know when acquisition started in febcontrol and list, indentation as well
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2015-05-20 12:01:49 +02:00 |
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Dhanya Maliakal
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d658799b20
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eiger reading master slave top bottom configuration from firmware;not reading from file anymore, serial is hardcoded for each master: also bug changes in gui getting frame from receiver in postprocessing
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2015-02-23 15:18:02 +01:00 |
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Maliakal Dhanya
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4649de2742
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some changes for better testing in eiger server, including using set receiver, and changed to top/bottom instead of master slave
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2014-11-28 14:26:19 +01:00 |
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Maliakal Dhanya
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194b41bfc5
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changes to get index in eiger server
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2014-11-17 14:46:28 +01:00 |
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Maliakal Dhanya
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bbf26927dd
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full module server works now, slave and master yet to be done
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2014-10-14 15:38:45 +02:00 |
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Maliakal Dhanya
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d8c7201749
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module udpport2
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2014-09-26 11:18:59 +02:00 |
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Maliakal Dhanya
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7faac70c3f
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trimbits work.
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2014-09-09 15:42:16 +02:00 |
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Maliakal Dhanya
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c5a4f357bf
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got rid of extra servers for eiger, converted to c and it works
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2014-08-29 16:41:19 +02:00 |
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Maliakal Dhanya
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56da3f42cc
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trimbits not working yet, nth frame works for eiger, scans work for eiger
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2014-07-31 12:11:33 +02:00 |
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Maliakal Dhanya
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de319249cd
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latest update from Ian in eiger server
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2014-05-27 15:03:08 +02:00 |
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