304 Commits

Author	SHA1	Message	Date
Marie Andrä	6e6fcec698	MY3.0:read and write Registers, frames, cycles, delay (#64) ... * MY3.0:read and write Registers, frames, cycles, delay * write pattern seems to work * done all corrections. added default clks: run_clk=125MHz, tick_clk=20MHz (fix), sampling_clk=80MHz (from Carlos) * clk check for aquistition time * clk check for aquistition time * Update slsDetectorServer_defs.h * Update slsDetectorFunctionList.c	2019-09-30 14:36:33 +02:00
Marie Andrä	4b987abf41	Niosmarie (#63) ... * HV for Mythen3 server * HV for mythen3 server * corrected upstreams * missing endif	2019-09-03 09:36:02 +02:00
Dhanya Thattil	40b62ef5a4	recompiled binaries	2019-09-02 19:31:36 +02:00
Dhanya Thattil	cb8c7eea54	updated binaries	2019-08-30 11:26:23 +02:00