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jungfrau server: changes for old and new boards

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This commit is contained in:
maliakal_d 2019-07-30 09:32:10 +02:00
parent 64a8dd2def
commit facbc60907
8 changed files with 98 additions and 80 deletions
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15
slsDetectorServers/jungfrauDetectorServer/RegisterDefs.h
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@ -6,8 +6,8 @@
/* FPGA Version register */
#define FPGA_VERSION_REG (0x00 << MEM_MAP_SHIFT)
#define BOARD_REVISION_OFST (0)
#define BOARD_REVISION_MSK (0x00FFFFFF << BOARD_REVISION_OFST)
#define FPGA_COMPILATION_DATE_OFST (0)
#define FPGA_COMPILATION_DATE_MSK (0x00FFFFFF << FPGA_COMPILATION_DATE_OFST)
#define DETECTOR_TYPE_OFST (24)
#define DETECTOR_TYPE_MSK (0x000000FF << DETECTOR_TYPE_OFST)
@ -56,12 +56,13 @@
/* Module Control Board Serial Number Register */
#define MOD_SERIAL_NUM_REG (0x0A << MEM_MAP_SHIFT) //Not used in software
#define MOD_SERIAL_NUM_REG (0x0A << MEM_MAP_SHIFT)
#define HARDWARE_SERIAL_NUM_OFST (0) //Not used in software
#define HARDWARE_SERIAL_NUM_MSK (0x000000FF << HARDWARE_SERIAL_NUM_OFST) //Not used in software
#define HARDWARE_VERSION_NUM_OFST (16) //Not used in software
#define HARDWARE_VERSION_NUM_MSK (0x0000003F << HARDWARE_VERSION_NUM_OFST) //Not used in software
#define HARDWARE_SERIAL_NUM_OFST (0)
#define HARDWARE_SERIAL_NUM_MSK (0x000000FF << HARDWARE_SERIAL_NUM_OFST)
#define HARDWARE_VERSION_NUM_OFST (16)
#define HARDWARE_VERSION_NUM_MSK (0x0000003F << HARDWARE_VERSION_NUM_OFST)
#define HARDWARE_VERSION_2_VAL ((0x2 << HARDWARE_VERSION_NUM_OFST) & HARDWARE_VERSION_NUM_MSK)
/* API Version Register */

BIN
slsDetectorServers/jungfrauDetectorServer/bin/jungfrauDetectorServer_developer
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Binary file not shown.

99
slsDetectorServers/jungfrauDetectorServer/slsDetectorFunctionList.c
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@ -91,6 +91,7 @@ void basictests() {
int64_t swversion = getDetectorId(DETECTOR_SOFTWARE_VERSION);
int64_t sw_fw_apiversion = 0;
int64_t client_sw_apiversion = getDetectorId(CLIENT_SOFTWARE_API_VERSION);
uint32_t requiredFirmwareVersion = (isHardwareVersion2() ? REQRD_FRMWRE_VRSN_BOARD2 : REQRD_FRMWRE_VRSN);
if (fwversion >= MIN_REQRD_VRSN_T_RD_API)
@ -114,7 +115,7 @@ void basictests() {
(long long int)fwversion,
(long long int)swversion,
(long long int)sw_fw_apiversion,
REQRD_FRMWR_VRSN,
requiredFirmwareVersion,
(long long int)client_sw_apiversion
));
@ -137,12 +138,12 @@ void basictests() {
}
//check for API compatibility - old server
if(sw_fw_apiversion > REQRD_FRMWR_VRSN){
if(sw_fw_apiversion > requiredFirmwareVersion){
sprintf(firmware_message,
"This detector software software version (0x%llx) is incompatible.\n"
"Please update detector software (min. 0x%llx) to be compatible with this firmware.\n",
(long long int)sw_fw_apiversion,
(long long int)REQRD_FRMWR_VRSN);
(long long int)requiredFirmwareVersion);
FILE_LOG(logERROR, (firmware_message));
firmware_compatibility = FAIL;
firmware_check_done = 1;
@ -150,12 +151,12 @@ void basictests() {
}
//check for firmware compatibility - old firmware
if( REQRD_FRMWR_VRSN > fwversion) {
if( requiredFirmwareVersion > fwversion) {
sprintf(firmware_message,
"This firmware version (0x%llx) is incompatible.\n"
"Please update firmware (min. 0x%llx) to be compatible with this server.\n",
(long long int)fwversion,
(long long int)REQRD_FRMWR_VRSN);
(long long int)requiredFirmwareVersion);
FILE_LOG(logERROR, (firmware_message));
firmware_compatibility = FAIL;
firmware_check_done = 1;
@ -275,7 +276,7 @@ u_int64_t getFirmwareVersion() {
#ifdef VIRTUAL
return 0;
#endif
return ((bus_r(FPGA_VERSION_REG) & BOARD_REVISION_MSK) >> BOARD_REVISION_OFST);
return ((bus_r(FPGA_VERSION_REG) & FPGA_COMPILATION_DATE_MSK) >> FPGA_COMPILATION_DATE_OFST);
}
u_int64_t getFirmwareAPIVersion() {
@ -299,6 +300,10 @@ u_int16_t getHardwareSerialNumber() {
return ((bus_r(MOD_SERIAL_NUM_REG) & HARDWARE_SERIAL_NUM_MSK) >> HARDWARE_SERIAL_NUM_OFST);
}
int isHardwareVersion2() {
return (((bus_r(MOD_SERIAL_NUM_REG) & HARDWARE_VERSION_NUM_MSK) == HARDWARE_VERSION_2_VAL) ? 1 : 0 );
}
u_int32_t getDetectorNumber(){
#ifdef VIRTUAL
return 0;
@ -424,7 +429,7 @@ void setupDetector() {
alignDeserializer();
configureASICTimer();
bus_w(ADC_PORT_INVERT_REG, ADC_PORT_INVERT_VAL);
bus_w(ADC_PORT_INVERT_REG, (isHardwareVersion2() ? ADC_PORT_INVERT_BOARD2_VAL : ADC_PORT_INVERT_VAL));
initReadoutConfiguration();
@ -1357,60 +1362,60 @@ void setClockDivider(int val) {
if(val >= 0) {
// stop state machine if running
if(runBusy())
if(runBusy()) {
stopStateMachine();
}
uint32_t adcOfst = 0;
uint32_t sampleAdcSpeed = 0;
uint32_t adcPhase = 0;
uint32_t config = CONFIG_FULL_SPEED_40MHZ_VAL;
switch(val) {
case FULL_SPEED:
FILE_LOG(logINFO, ("Setting Full Speed (40 MHz):\n"));
if(isHardwareVersion2()) {
FILE_LOG(logERROR, ("Cannot set full speed. Should not be here\n"));
return;
}
FILE_LOG(logINFO, ("Setting Full Speed (40 MHz):\n"));
adcOfst = ADC_OFST_FULL_SPEED_VAL;
sampleAdcSpeed = SAMPLE_ADC_FULL_SPEED;
adcPhase = ADC_PHASE_FULL_SPEED;
config = CONFIG_FULL_SPEED_40MHZ_VAL;
break;
bus_w(SAMPLE_REG, SAMPLE_ADC_FULL_SPEED);
FILE_LOG(logINFO, ("\tSet Sample Reg to 0x%x\n", bus_r(SAMPLE_REG)));
bus_w(CONFIG_REG, (bus_r(CONFIG_REG) & ~CONFIG_READOUT_SPEED_MSK) | CONFIG_FULL_SPEED_40MHZ_VAL);
FILE_LOG(logINFO, ("\tSet Config Reg to 0x%x\n", bus_r(CONFIG_REG)));
bus_w(ADC_OFST_REG, ADC_OFST_FULL_SPEED_VAL);
FILE_LOG(logINFO, ("\tSet ADC Ofst Reg to 0x%x\n", bus_r(ADC_OFST_REG)));
setAdcPhase(ADC_PHASE_FULL_SPEED, 0);
FILE_LOG(logINFO, ("\tSet ADC Phase Reg to %d\n", ADC_PHASE_FULL_SPEED));
break;
case HALF_SPEED:
case HALF_SPEED:
FILE_LOG(logINFO, ("Setting Half Speed (20 MHz):\n"));
adcOfst = isHardwareVersion2() ? ADC_OFST_HALF_SPEED_BOARD2_VAL : ADC_OFST_HALF_SPEED_VAL;
sampleAdcSpeed = isHardwareVersion2() ? SAMPLE_ADC_HALF_SPEED_BOARD2 : SAMPLE_ADC_HALF_SPEED;
adcPhase = isHardwareVersion2() ? ADC_PHASE_HALF_SPEED_BOARD2 : ADC_PHASE_HALF_SPEED;
config = CONFIG_HALF_SPEED_20MHZ_VAL;
break;
bus_w(SAMPLE_REG, SAMPLE_ADC_HALF_SPEED);
FILE_LOG(logINFO, ("\tSet Sample Reg to 0x%x\n", bus_r(SAMPLE_REG)));
bus_w(CONFIG_REG, (bus_r(CONFIG_REG) & ~CONFIG_READOUT_SPEED_MSK) | CONFIG_HALF_SPEED_20MHZ_VAL);
FILE_LOG(logINFO, ("\tSet Config Reg to 0x%x\n", bus_r(CONFIG_REG)));
bus_w(ADC_OFST_REG, ADC_OFST_HALF_SPEED_VAL);
FILE_LOG(logINFO, ("\tSet ADC Ofst Reg to 0x%x\n", bus_r(ADC_OFST_REG)));
setAdcPhase(ADC_PHASE_HALF_SPEED, 0);
FILE_LOG(logINFO, ("\tSet ADC Phase Reg to %d\n", ADC_PHASE_HALF_SPEED));
break;
case QUARTER_SPEED:
case QUARTER_SPEED:
FILE_LOG(logINFO, ("Setting Half Speed (10 MHz):\n"));
adcOfst = isHardwareVersion2() ? ADC_OFST_QUARTER_SPEED_BOARD2_VAL : ADC_OFST_QUARTER_SPEED_VAL;
sampleAdcSpeed = isHardwareVersion2() ? SAMPLE_ADC_QUARTER_SPEED_BOARD2 : SAMPLE_ADC_QUARTER_SPEED;
adcPhase = isHardwareVersion2() ? ADC_PHASE_QUARTER_SPEED_BOARD2 : ADC_PHASE_QUARTER_SPEED;
config = CONFIG_QUARTER_SPEED_10MHZ_VAL;
break;
bus_w(SAMPLE_REG, SAMPLE_ADC_QUARTER_SPEED);
FILE_LOG(logINFO, ("\tSet Sample Reg to 0x%x\n", bus_r(SAMPLE_REG)));
default:
break;
}
bus_w(CONFIG_REG, (bus_r(CONFIG_REG) & ~CONFIG_READOUT_SPEED_MSK) | CONFIG_QUARTER_SPEED_10MHZ_VAL);
FILE_LOG(logINFO, ("\tSet Config Reg to 0x%x\n", bus_r(CONFIG_REG)));
bus_w(CONFIG_REG, (bus_r(CONFIG_REG) & ~CONFIG_READOUT_SPEED_MSK) | config);
FILE_LOG(logINFO, ("\tSet Config Reg to 0x%x\n", bus_r(CONFIG_REG)));
bus_w(ADC_OFST_REG, ADC_OFST_QUARTER_SPEED_VAL);
FILE_LOG(logINFO, ("\tSet ADC Ofst Reg to 0x%x\n", bus_r(ADC_OFST_REG)));
bus_w(ADC_OFST_REG, adcOfst);
FILE_LOG(logINFO, ("\tSet ADC Ofst Reg to 0x%x\n", bus_r(ADC_OFST_REG)));
setAdcPhase(ADC_PHASE_QUARTER_SPEED, 0);
FILE_LOG(logINFO, ("\tSet ADC Phase Reg to %d\n", ADC_PHASE_QUARTER_SPEED));
break;
bus_w(SAMPLE_REG, sampleAdcSpeed);
FILE_LOG(logINFO, ("\tSet Sample Reg to 0x%x\n", bus_r(SAMPLE_REG)));
}
setAdcPhase(adcPhase, 0);
FILE_LOG(logINFO, ("\tSet ADC Phase Reg to %d\n", adcPhase));
}
}

45
slsDetectorServers/jungfrauDetectorServer/slsDetectorServer_defs.h
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@ -4,7 +4,8 @@
#define MIN_REQRD_VRSN_T_RD_API 0x171220
#define REQRD_FRMWR_VRSN 0x190708
#define REQRD_FRMWRE_VRSN_BOARD2 0x190716
#define REQRD_FRMWRE_VRSN 0x190708
#define CTRL_SRVR_INIT_TIME_US (300 * 1000)
@ -89,23 +90,31 @@ enum NETWORKINDEX { TXN_FRAME, FLOWCTRL_10G };
#define MAX_STORAGE_CELL_DLY_NS_VAL ((ASIC_CTRL_EXPSRE_TMR_MSK >> ASIC_CTRL_EXPSRE_TMR_OFST) * ASIC_CTRL_EXPSRE_TMR_STEPS)
#define ACQ_TIME_MIN_CLOCK (2)
#define BOARD_VERSION_2_VAL (0x3F)
#define SAMPLE_ADC_FULL_SPEED (SAMPLE_ADC_SAMPLE_0_VAL + SAMPLE_ADC_DECMT_FACTOR_0_VAL + SAMPLE_DGTL_SAMPLE_3_VAL + SAMPLE_DECMT_FACTOR_FULL_VAL) // 0x300
#define SAMPLE_ADC_HALF_SPEED (SAMPLE_ADC_SAMPLE_0_VAL + SAMPLE_ADC_DECMT_FACTOR_1_VAL + SAMPLE_DGTL_SAMPLE_6_VAL + SAMPLE_DECMT_FACTOR_HALF_VAL) // 0x1610
#define SAMPLE_ADC_QUARTER_SPEED (SAMPLE_ADC_SAMPLE_0_VAL + SAMPLE_ADC_DECMT_FACTOR_3_VAL + SAMPLE_DGTL_SAMPLE_11_VAL + SAMPLE_DECMT_FACTOR_QUARTER_VAL) // 0x2b30
#define ADC_OFST_FULL_SPEED_VAL (0xF)
#define ADC_OFST_HALF_SPEED_VAL (0xB)
#define ADC_OFST_QUARTER_SPEED_VAL (0x7)
#define ADC_PHASE_FULL_SPEED (0x1E) //30
#define ADC_PHASE_HALF_SPEED (0x1E) //30
#define ADC_PHASE_QUARTER_SPEED (0x1E) //30
#define ADC_PORT_INVERT_VAL (0x5A5A5A5A)//(0x453b2a9c)
#define MAX_PHASE_SHIFTS (160)
#define BIT16_MASK (0xFFFF)
#define UDP_IP_HEADER_LENGTH_BYTES (28)
#define ADC_OFST_FULL_SPEED_VAL (0xf)
#define ADC_OFST_HALF_SPEED_VAL (0xb)
#define ADC_OFST_QUARTER_SPEED_VAL (0x7)
#define ADC_OFST_HALF_SPEED_BOARD2_VAL (0x13)
#define ADC_OFST_QUARTER_SPEED_BOARD2_VAL (0x0b)
#define ADC_PORT_INVERT_VAL (0x5A5A5A5A)
#define ADC_PORT_INVERT_BOARD2_VAL (0x453b2a9c)
#define SAMPLE_ADC_FULL_SPEED (SAMPLE_ADC_SAMPLE_0_VAL + SAMPLE_ADC_DECMT_FACTOR_0_VAL + SAMPLE_DGTL_SAMPLE_3_VAL + SAMPLE_DECMT_FACTOR_FULL_VAL) // 0x300
#define SAMPLE_ADC_HALF_SPEED (SAMPLE_ADC_SAMPLE_0_VAL + SAMPLE_ADC_DECMT_FACTOR_1_VAL + SAMPLE_DGTL_SAMPLE_6_VAL + SAMPLE_DECMT_FACTOR_HALF_VAL) // 0x1610
#define SAMPLE_ADC_QUARTER_SPEED (SAMPLE_ADC_SAMPLE_0_VAL + SAMPLE_ADC_DECMT_FACTOR_3_VAL + SAMPLE_DGTL_SAMPLE_11_VAL + SAMPLE_DECMT_FACTOR_QUARTER_VAL) // 0x2b30
#define SAMPLE_ADC_HALF_SPEED_BOARD2 (SAMPLE_ADC_SAMPLE_0_VAL + SAMPLE_ADC_DECMT_FACTOR_0_VAL + SAMPLE_DGTL_SAMPLE_6_VAL + SAMPLE_DECMT_FACTOR_HALF_VAL) // 0x1600
#define SAMPLE_ADC_QUARTER_SPEED_BOARD2 (SAMPLE_ADC_SAMPLE_0_VAL + SAMPLE_ADC_DECMT_FACTOR_1_VAL + SAMPLE_DGTL_SAMPLE_11_VAL + SAMPLE_DECMT_FACTOR_QUARTER_VAL) // 0x2b10
#define ADC_PHASE_FULL_SPEED (0x1E) //30
#define ADC_PHASE_HALF_SPEED (0x1E) //30
#define ADC_PHASE_QUARTER_SPEED (0x1E) //30
#define ADC_PHASE_HALF_SPEED_BOARD2 (0x1E) //30
#define ADC_PHASE_QUARTER_SPEED_BOARD2 (0x1E) //30

3
slsDetectorServers/slsDetectorServer/slsDetectorFunctionList.h
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@ -39,6 +39,9 @@ u_int64_t getFirmwareAPIVersion();
u_int16_t getHardwareVersionNumber();
u_int16_t getHardwareSerialNumber();
#endif
#ifdef JUNGFRAUD
int isHardwareVersion2();
#endif
u_int32_t getDetectorNumber();
u_int64_t getDetectorMAC();
u_int32_t getDetectorIP();

2
slsDetectorServers/slsDetectorServer/slsDetectorServer_funcs.c
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@ -2012,7 +2012,7 @@ int set_speed(int file_des) {
}
#endif
#ifdef JUNGFRAUD
if (ret == OK && ind == CLOCK_DIVIDER && val == FULL_SPEED && getHardwareVersionNumber() != BOARD_VERSION_2_VAL) {
if (ret == OK && ind == CLOCK_DIVIDER && val == FULL_SPEED && isHardwareVersion2()) {
ret = FAIL;
strcpy(mess, "Full speed not implemented for this board version.\n");
FILE_LOG(logERROR,(mess));

4
slsDetectorSoftware/src/slsDetector.cpp
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@ -1925,7 +1925,7 @@ std::string slsDetector::getClientStreamingIP() { return shm()->zmqip.str(); }
void slsDetector::setReceiverStreamingIP(std::string sourceIP) {
// if empty, give rx_hostname
if (sourceIP.empty()) {
if (sourceIP.empty() || sourceIP == "0.0.0.0") {
if (strcmp(shm()->rxHostname, "none") == 0) {
throw RuntimeError("Receiver hostname not set yet. Cannot create "
"rx_zmqip from none");
@ -1947,7 +1947,7 @@ void slsDetector::setReceiverStreamingIP(std::string sourceIP) {
char retvals[MAX_STR_LENGTH]{};
char args[MAX_STR_LENGTH]{};
sls::strcpy_safe(args, shm()->rxZmqip.str()); // TODO send int
FILE_LOG(logDEBUG1)
FILE_LOG(logINFORED)
<< "Sending receiver streaming IP to receiver: " << args;
sendToReceiver(F_RECEIVER_STREAMING_SRC_IP, args, retvals);
FILE_LOG(logDEBUG1) << "Receiver streaming ip: " << retvals;

2
slsSupportLib/include/versionAPI.h
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@ -7,4 +7,4 @@
#define APILIB 0x190723
#define APIRECEIVER 0x190722
#define APIGUI 0x190723
#define APIJUNGFRAU 0x190724
#define APIJUNGFRAU 0x190730