From f9fff97f8a3d06f87c4b2d9fd11bf4cfa97458b1 Mon Sep 17 00:00:00 2001 From: Dhanya Thattil Date: Thu, 31 Oct 2019 14:48:53 +0100 Subject: [PATCH] mythen3 register mix up --- .../mythen3DetectorServer/RegisterDefs.h | 143 +++++++++++------- .../bin/mythen3DetectorServer_developer | Bin 123908 -> 123908 bytes 2 files changed, 86 insertions(+), 57 deletions(-) diff --git a/slsDetectorServers/mythen3DetectorServer/RegisterDefs.h b/slsDetectorServers/mythen3DetectorServer/RegisterDefs.h index 83731c5e2..e1bfe9600 100644 --- a/slsDetectorServers/mythen3DetectorServer/RegisterDefs.h +++ b/slsDetectorServers/mythen3DetectorServer/RegisterDefs.h @@ -1,20 +1,20 @@ -// stuff from Carlos #pragma once -/* Definitions for FPGA*/ +/* Base addresses */ #define REG_OFFSET (4) -#define BASE_CONTROL (0x0) -#define BASE_PATTERN_CONTROL (0x200) +#define BASE_CONTROL (0x0000) +#define BASE_PATTERN_CONTROL (0x00200) +#define BASE_UDP_RAM (0x01000) #define BASE_PATTERN_RAM (0x10000) -#define BASE_UDP_RAM (0x1000) // fix it -/* Basic detector FPGA registers --------------------------------------------------*/ +/* Control registers --------------------------------------------------*/ + /* Module Control Board Serial Number Register */ -#define MCB_SERIAL_NO_REG (0x000 * REG_OFFSET + BASE_CONTROL) +#define MCB_SERIAL_NO_REG (0x00 * REG_OFFSET + BASE_CONTROL) /* FPGA Version register */ -#define FPGA_VERSION_REG (0x001 * REG_OFFSET + BASE_CONTROL) +#define FPGA_VERSION_REG (0x01 * REG_OFFSET + BASE_CONTROL) #define FPGA_COMPILATION_DATE_OFST (0) #define FPGA_COMPILATION_DATE_MSK (0x00FFFFFF << FPGA_COMPILATION_DATE_OFST) @@ -23,7 +23,7 @@ /* API Version Register */ -#define API_VERSION_REG (0x002 * REG_OFFSET + BASE_CONTROL) +#define API_VERSION_REG (0x02 * REG_OFFSET + BASE_CONTROL) #define API_VERSION_OFST (0) #define API_VERSION_MSK (0x00FFFFFF << API_VERSION_OFST) @@ -31,22 +31,27 @@ #define API_VERSION_DETECTOR_TYPE_MSK (0x000000FF << API_VERSION_DETECTOR_TYPE_OFST) //Not used in software /* Fix pattern register */ -#define FIX_PATT_REG (0x003 * REG_OFFSET + BASE_CONTROL) +#define FIX_PATT_REG (0x03 * REG_OFFSET + BASE_CONTROL) #define FIX_PATT_VAL (0xACDC2019) /* Status register */ -#define STATUS_REG (0x004 * REG_OFFSET + BASE_CONTROL) +#define STATUS_REG (0x04 * REG_OFFSET + BASE_CONTROL) -#ifdef VIRTUAL // until firmware is ready ---------------------------------- +#ifdef VIRTUAL // until firmware is ready #define RUN_BUSY_OFST (0) #define RUN_BUSY_MSK (0x00000001 << RUN_BUSY_OFST) #endif /* Look at me register, read only */ -#define LOOK_AT_ME_REG (0x005 * REG_OFFSET + BASE_CONTROL) //Not used in firmware or software, good to play with +#define LOOK_AT_ME_REG (0x05 * REG_OFFSET + BASE_CONTROL) //Not used in firmware or software, good to play with + +#define SYSTEM_STATUS_REG (0x06 * REG_OFFSET + BASE_CONTROL) //Not used in software + +/* Config RW regiseter */ +#define CONFIG_REG (0x20 * REG_OFFSET + BASE_CONTROL) /* Control RW register */ // assumed for MY3 -#define CONTROL_REG (0x021 * REG_OFFSET + BASE_CONTROL) +#define CONTROL_REG (0x21 * REG_OFFSET + BASE_CONTROL) #define CONTROL_STRT_ACQSTN_OFST (0) #define CONTROL_STRT_ACQSTN_MSK (0x00000001 << CONTROL_STRT_ACQSTN_OFST) @@ -65,127 +70,151 @@ #define CONTROL_CLR_ACQSTN_FIFO_OFST (14) #define CONTROL_CLR_ACQSTN_FIFO_MSK (0x00000001 << CONTROL_CLR_ACQSTN_FIFO_OFST) +/* Pattern IO Control 64 bit register */ +#define PATTERN_IO_CTRL_LSB_REG (0x22 * REG_OFFSET + BASE_CONTROL) +#define PATTERN_IO_CTRL_MSB_REG (0x23 * REG_OFFSET + BASE_CONTROL) -#define DTA_OFFSET_REG (0x104 * REG_OFFSET + BASE_CONTROL) +#define DTA_OFFSET_REG (0x24 * REG_OFFSET + BASE_CONTROL) + + +/* Pattern Control registers --------------------------------------------------*/ -/* Pattern Control FPGA registers --------------------------------------------------*/ /* Pattern status Register*/ -#define PAT_STATUS_REG (0x000 * REG_OFFSET + BASE_PATTERN_CONTROL) +#define PAT_STATUS_REG (0x00 * REG_OFFSET + BASE_PATTERN_CONTROL) /* Delay left 64bit Register */ -#define GET_DELAY_LSB_REG (0x0002 * REG_OFFSET + BASE_PATTERN_CONTROL) -#define GET_DELAY_MSB_REG (0x0003 * REG_OFFSET + BASE_PATTERN_CONTROL) +#define GET_DELAY_LSB_REG (0x02 * REG_OFFSET + BASE_PATTERN_CONTROL) +#define GET_DELAY_MSB_REG (0x03 * REG_OFFSET + BASE_PATTERN_CONTROL) /* Triggers left 64bit Register */ -#define GET_CYCLES_LSB_REG (0x0004 * REG_OFFSET + BASE_PATTERN_CONTROL) -#define GET_CYCLES_MSB_REG (0x0005 * REG_OFFSET + BASE_PATTERN_CONTROL) +#define GET_CYCLES_LSB_REG (0x04 * REG_OFFSET + BASE_PATTERN_CONTROL) +#define GET_CYCLES_MSB_REG (0x05 * REG_OFFSET + BASE_PATTERN_CONTROL) /* Frames left 64bit Register */ -#define GET_FRAMES_LSB_REG (0x0006 * REG_OFFSET + BASE_PATTERN_CONTROL) -#define GET_FRAMES_MSB_REG (0x0007 * REG_OFFSET + BASE_PATTERN_CONTROL) +#define GET_FRAMES_LSB_REG (0x06 * REG_OFFSET + BASE_PATTERN_CONTROL) +#define GET_FRAMES_MSB_REG (0x07 * REG_OFFSET + BASE_PATTERN_CONTROL) /* Period left 64bit Register */ -#define GET_PERIOD_LSB_REG (0x0008 * REG_OFFSET + BASE_PATTERN_CONTROL) -#define GET_PERIOD_MSB_REG (0x0009 * REG_OFFSET + BASE_PATTERN_CONTROL) +#define GET_PERIOD_LSB_REG (0x08 * REG_OFFSET + BASE_PATTERN_CONTROL) +#define GET_PERIOD_MSB_REG (0x09 * REG_OFFSET + BASE_PATTERN_CONTROL) +/* Time from Start 64 bit register */ +#define TIME_FROM_START_LSB_REG (0x0A * REG_OFFSET + BASE_PATTERN_CONTROL) +#define TIME_FROM_START_MSB_REG (0x0B * REG_OFFSET + BASE_PATTERN_CONTROL) + +/* Get Frames from Start 64 bit register (frames from last reset using CONTROL_CRST) */ +#define FRAMES_FROM_START_LSB_REG (0x0C * REG_OFFSET + BASE_PATTERN_CONTROL) +#define FRAMES_FROM_START_MSB_REG (0x0D * REG_OFFSET + BASE_PATTERN_CONTROL) + +/* Measurement Time 64 bit register (timestamp at a frame start until reset)*/ +#define START_FRAME_TIME_LSB_REG (0x0E * REG_OFFSET + BASE_PATTERN_CONTROL) +#define START_FRAME_TIME_MSB_REG (0x0F * REG_OFFSET + BASE_PATTERN_CONTROL) /* Delay 64bit Write-register */ -#define SET_DELAY_LSB_REG (0x0102 * REG_OFFSET + BASE_PATTERN_CONTROL) -#define SET_DELAY_MSB_REG (0x0103 * REG_OFFSET + BASE_PATTERN_CONTROL) +#define SET_DELAY_LSB_REG (0x22 * REG_OFFSET + BASE_PATTERN_CONTROL) +#define SET_DELAY_MSB_REG (0x23 * REG_OFFSET + BASE_PATTERN_CONTROL) /* Cylces 64bit Write-register */ -#define SET_CYCLES_LSB_REG (0x0104 * REG_OFFSET + BASE_PATTERN_CONTROL) -#define SET_CYCLES_MSB_REG (0x0105 * REG_OFFSET + BASE_PATTERN_CONTROL) +#define SET_CYCLES_LSB_REG (0x24 * REG_OFFSET + BASE_PATTERN_CONTROL) +#define SET_CYCLES_MSB_REG (0x25 * REG_OFFSET + BASE_PATTERN_CONTROL) /* Frames 64bit Write-register */ -#define SET_FRAMES_LSB_REG (0x0106 * REG_OFFSET + BASE_PATTERN_CONTROL) -#define SET_FRAMES_MSB_REG (0x0107 * REG_OFFSET + BASE_PATTERN_CONTROL) +#define SET_FRAMES_LSB_REG (0x26 * REG_OFFSET + BASE_PATTERN_CONTROL) +#define SET_FRAMES_MSB_REG (0x27 * REG_OFFSET + BASE_PATTERN_CONTROL) /* Period 64bit Write-register */ -#define SET_PERIOD_LSB_REG (0x0108 * REG_OFFSET + BASE_PATTERN_CONTROL) -#define SET_PERIOD_MSB_REG (0x0109 * REG_OFFSET + BASE_PATTERN_CONTROL) +#define SET_PERIOD_LSB_REG (0x28 * REG_OFFSET + BASE_PATTERN_CONTROL) +#define SET_PERIOD_MSB_REG (0x29 * REG_OFFSET + BASE_PATTERN_CONTROL) +/* External Signal register */ +#define EXT_SIGNAL_REG (0x30 * REG_OFFSET + BASE_PATTERN_CONTROL) -/* Pattern Control FPGA registers --------------------------------------------------*/ - -// /* Pattern IO Control 64 bit RW Register -// * Each bit configured as output(1)/ input(0) */ -// #define PATTERN_IO_CNTRL_LSB_REG (0x88 + BASE_CONTROL) -// #define PATTERN_IO_CNTRL_MSB_REG (0x8C + BASE_CONTROL) +/* Trigger Delay 64 bit register */ +#define SET_TRIGGER_DELAY_LSB_REG (0x32 * REG_OFFSET + BASE_PATTERN_CONTROL) +#define SET_TRIGGER_DELAY_MSB_REG (0x33 * REG_OFFSET + BASE_PATTERN_CONTROL) /* Pattern Limit RW Register */ -#define PATTERN_LIMIT_REG (0x1000 * REG_OFFSET + BASE_PATTERN_CONTROL) +#define PATTERN_LIMIT_REG (0x40 * REG_OFFSET + BASE_PATTERN_CONTROL) #define PATTERN_LIMIT_STRT_OFST (0) #define PATTERN_LIMIT_STRT_MSK (0x00001FFF << PATTERN_LIMIT_STRT_OFST) #define PATTERN_LIMIT_STP_OFST (16) #define PATTERN_LIMIT_STP_MSK (0x00001FFF << PATTERN_LIMIT_STP_OFST) +/** Pattern Mask 64 bit RW regiser */ +#define PATTERN_MASK_LSB_REG (0x42 * REG_OFFSET + BASE_PATTERN_CONTROL) +#define PATTERN_MASK_MSB_REG (0x43 * REG_OFFSET + BASE_PATTERN_CONTROL) + +/** Pattern Set 64 bit RW regiser */ +#define PATTERN_SET_LSB_REG (0x44 * REG_OFFSET + BASE_PATTERN_CONTROL) +#define PATTERN_SET_MSB_REG (0x45 * REG_OFFSET + BASE_PATTERN_CONTROL) + /* Pattern Wait Timer 0 64bit RW Register */ -#define PATTERN_WAIT_TIMER_0_LSB_REG (0x1100 * REG_OFFSET + BASE_PATTERN_CONTROL) -#define PATTERN_WAIT_TIMER_0_MSB_REG (0x1101 * REG_OFFSET + BASE_PATTERN_CONTROL) +#define PATTERN_WAIT_TIMER_0_LSB_REG (0x60 * REG_OFFSET + BASE_PATTERN_CONTROL) +#define PATTERN_WAIT_TIMER_0_MSB_REG (0x61 * REG_OFFSET + BASE_PATTERN_CONTROL) /* Pattern Wait 0 RW Register*/ -#define PATTERN_WAIT_0_ADDR_REG (0x1102 * REG_OFFSET + BASE_PATTERN_CONTROL) +#define PATTERN_WAIT_0_ADDR_REG (0x62 * REG_OFFSET + BASE_PATTERN_CONTROL) #define PATTERN_WAIT_0_ADDR_OFST (0) #define PATTERN_WAIT_0_ADDR_MSK (0x00001FFF << PATTERN_WAIT_0_ADDR_OFST) /* Pattern Loop 0 Iteration RW Register */ -#define PATTERN_LOOP_0_ITERATION_REG (0x1103 * REG_OFFSET + BASE_PATTERN_CONTROL) // patnloop +#define PATTERN_LOOP_0_ITERATION_REG (0x63 * REG_OFFSET + BASE_PATTERN_CONTROL) /* Pattern Loop 0 Address RW Register */ -#define PATTERN_LOOP_0_ADDR_REG (0x1104 * REG_OFFSET + BASE_PATTERN_CONTROL) +#define PATTERN_LOOP_0_ADDR_REG (0x64 * REG_OFFSET + BASE_PATTERN_CONTROL) #define PATTERN_LOOP_0_ADDR_STRT_OFST (0) #define PATTERN_LOOP_0_ADDR_STRT_MSK (0x00001FFF << PATTERN_LOOP_0_ADDR_STRT_OFST) #define PATTERN_LOOP_0_ADDR_STP_OFST (16) #define PATTERN_LOOP_0_ADDR_STP_MSK (0x00001FFF << PATTERN_LOOP_0_ADDR_STP_OFST) - /* Pattern Wait Timer 1 64bit RW Register */ -#define PATTERN_WAIT_TIMER_1_LSB_REG (0x1105 * REG_OFFSET + BASE_PATTERN_CONTROL) -#define PATTERN_WAIT_TIMER_1_MSB_REG (0x1106 * REG_OFFSET + BASE_PATTERN_CONTROL) +#define PATTERN_WAIT_TIMER_1_LSB_REG (0x65 * REG_OFFSET + BASE_PATTERN_CONTROL) +#define PATTERN_WAIT_TIMER_1_MSB_REG (0x66 * REG_OFFSET + BASE_PATTERN_CONTROL) /* Pattern Wait 1 RW Register*/ -#define PATTERN_WAIT_1_ADDR_REG (0x1107 * REG_OFFSET + BASE_PATTERN_CONTROL) +#define PATTERN_WAIT_1_ADDR_REG (0x67 * REG_OFFSET + BASE_PATTERN_CONTROL) #define PATTERN_WAIT_1_ADDR_OFST (0) #define PATTERN_WAIT_1_ADDR_MSK (0x00001FFF << PATTERN_WAIT_1_ADDR_OFST) /* Pattern Loop 1 Iteration RW Register */ -#define PATTERN_LOOP_1_ITERATION_REG (0x1108 * REG_OFFSET + BASE_PATTERN_CONTROL) // patnloop +#define PATTERN_LOOP_1_ITERATION_REG (0x68 * REG_OFFSET + BASE_PATTERN_CONTROL) /* Pattern Loop 1 Address RW Register */ -#define PATTERN_LOOP_1_ADDR_REG (0x1109 * REG_OFFSET + BASE_PATTERN_CONTROL) +#define PATTERN_LOOP_1_ADDR_REG (0x69 * REG_OFFSET + BASE_PATTERN_CONTROL) #define PATTERN_LOOP_1_ADDR_STRT_OFST (0) #define PATTERN_LOOP_1_ADDR_STRT_MSK (0x00001FFF << PATTERN_LOOP_1_ADDR_STRT_OFST) #define PATTERN_LOOP_1_ADDR_STP_OFST (16) #define PATTERN_LOOP_1_ADDR_STP_MSK (0x00001FFF << PATTERN_LOOP_1_ADDR_STP_OFST) - /* Pattern Wait Timer 2 64bit RW Register */ -#define PATTERN_WAIT_TIMER_2_LSB_REG (0x110A * REG_OFFSET + BASE_PATTERN_CONTROL) -#define PATTERN_WAIT_TIMER_2_MSB_REG (0x110B * REG_OFFSET + BASE_PATTERN_CONTROL) +#define PATTERN_WAIT_TIMER_2_LSB_REG (0x6A * REG_OFFSET + BASE_PATTERN_CONTROL) +#define PATTERN_WAIT_TIMER_2_MSB_REG (0x6B * REG_OFFSET + BASE_PATTERN_CONTROL) /* Pattern Wait 2 RW Register*/ -#define PATTERN_WAIT_2_ADDR_REG (0x110C * REG_OFFSET + BASE_PATTERN_CONTROL) +#define PATTERN_WAIT_2_ADDR_REG (0x6C * REG_OFFSET + BASE_PATTERN_CONTROL) #define PATTERN_WAIT_2_ADDR_OFST (0) #define PATTERN_WAIT_2_ADDR_MSK (0x00001FFF << PATTERN_WAIT_2_ADDR_OFST) /* Pattern Loop 2 Iteration RW Register */ -#define PATTERN_LOOP_2_ITERATION_REG (0x110D * REG_OFFSET + BASE_PATTERN_CONTROL) // patnloop +#define PATTERN_LOOP_2_ITERATION_REG (0x6D * REG_OFFSET + BASE_PATTERN_CONTROL) /* Pattern Loop 0 Address RW Register */ -#define PATTERN_LOOP_2_ADDR_REG (0x110E * REG_OFFSET + BASE_PATTERN_CONTROL) +#define PATTERN_LOOP_2_ADDR_REG (0x6E * REG_OFFSET + BASE_PATTERN_CONTROL) #define PATTERN_LOOP_2_ADDR_STRT_OFST (0) #define PATTERN_LOOP_2_ADDR_STRT_MSK (0x00001FFF << PATTERN_LOOP_2_ADDR_STRT_OFST) #define PATTERN_LOOP_2_ADDR_STP_OFST (16) #define PATTERN_LOOP_2_ADDR_STP_MSK (0x00001FFF << PATTERN_LOOP_2_ADDR_STP_OFST) + +/* Pattern RAM registers --------------------------------------------------*/ + /* Register of first word */ #define PATTERN_STEP0_LSB_REG (0x0 * REG_OFFSET + BASE_PATTERN_RAM) #define PATTERN_STEP0_MSB_REG (0x1 * REG_OFFSET + BASE_PATTERN_RAM) diff --git a/slsDetectorServers/mythen3DetectorServer/bin/mythen3DetectorServer_developer b/slsDetectorServers/mythen3DetectorServer/bin/mythen3DetectorServer_developer index 1daa8df8fad6d09af231db08c4cacfaafd27dcd5..be16f1f3ce8d22c8cb42eef7cd30af1796c1295a 100755 GIT binary patch delta 226 zcmZoU!QOI$eS@zwlS;#8f9Yo&Y|9TYvMg)ZY^`#RiESm2y`o_=zj_}N+fpEVNyB7o z6{XEbHJ=C=J!)VO{kH#s=y&@ENB*}ni2m6BfK7sdf#o?CaUr1in}*G|t?U?$9zf(- z9s=p_Kt19>xu;OEXHYSa`d3h~*A1J!ZJsf5JpuCH?|;DZ80ZE&HLjOX?u&-W*+A|) ZDEDo{mUb-SLO}7JiJNa**)bY5K;&5( zf%JEv9&w;tD^#ovDh5*D1r_U_xY^t086#H-A74HKFV+igE=$LP2e02MA=HUIzs