mirror of
https://github.com/slsdetectorgroup/slsDetectorPackage.git
synced 2025-06-23 18:17:59 +02:00
fix in ltc, added moench, separated servers, left to do max1932, client side for moench and more detailed in ctb server side
This commit is contained in:
@ -1,11 +1,7 @@
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#pragma once
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/* Definitions for FPGA */
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#ifdef JCTB
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#define MEM_MAP_SHIFT 11
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#else
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#define MEM_MAP_SHIFT 1
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#endif
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/* FPGA Version RO register */
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#define FPGA_VERSION_REG (0x00 << MEM_MAP_SHIFT)
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@ -14,7 +10,6 @@
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#define FPGA_VERSION_BRD_RVSN_MSK (0x00FFFFFF << FPGA_VERSION_BRD_RVSN_OFST)
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#define FPGA_VERSION_DTCTR_TYP_OFST (24)
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#define FPGA_VERSION_DTCTR_TYP_MSK (0x000000FF << FPGA_VERSION_DTCTR_TYP_OFST)
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#define FPGA_VERSION_DTCTR_TYP_JCTB_VAL ((0x2 << FPGA_VERSION_DTCTR_TYP_OFST) & FPGA_VERSION_DTCTR_TYP_MSK)
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#define FPGA_VERSION_DTCTR_TYP_CTB_VAL ((0x3 << FPGA_VERSION_DTCTR_TYP_OFST) & FPGA_VERSION_DTCTR_TYP_MSK)
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/* Fix pattern RO register */
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@ -64,7 +64,7 @@ void basictests() {
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firmware_check_done = 0;
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memset(firmware_message, 0, MAX_STR_LENGTH);
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#ifdef VIRTUAL
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FILE_LOG(logINFOBLUE, ("******** %s Virtual Server *****************\n", DETNAME));
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FILE_LOG(logINFOBLUE, ("******** Chip Test Board Virtual Server *****************\n"));
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if (mapCSP0() == FAIL) {
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strcpy(firmware_message,
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"Could not map to memory. Dangerous to continue.\n");
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@ -110,7 +110,7 @@ void basictests() {
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if (fwversion >= MIN_REQRD_VRSN_T_RD_API)
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sw_fw_apiversion = getDetectorId(SOFTWARE_FIRMWARE_API_VERSION);
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FILE_LOG(logINFOBLUE, ("************ %s Server *********************\n"
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FILE_LOG(logINFOBLUE, ("************ Chip Test Board Server *********************\n"
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"Hardware Version:\t\t 0x%x\n"
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"Hardware Serial Nr:\t\t 0x%x\n"
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@ -123,7 +123,6 @@ void basictests() {
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"Required Firmware Version:\t 0x%x\n"
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"Client-Software API Version:\t 0x%llx\n"
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"********************************************************\n",
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DETNAME,
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hversion, hsnumber,
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ipadd,
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(long long unsigned int)macadd,
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@ -189,13 +188,10 @@ int checkType() {
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uint32_t type = ((bus_r(FPGA_VERSION_REG) & FPGA_VERSION_DTCTR_TYP_MSK) >> FPGA_VERSION_DTCTR_TYP_OFST);
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uint32_t expectedType = FPGA_VERSION_DTCTR_TYP_CTB_VAL;
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#ifdef JCTB
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expectedType = FPGA_VERSION_DTCTR_TYP_JCTB_VAL;
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#endif
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if (type != expectedType) {
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FILE_LOG(logERROR, ("This is not a %s Server (read %d, expected %d)\n",
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DETNAME, type, expectedType));
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FILE_LOG(logERROR, ("This is not a Chip Test Board Server (read %d, expected %d)\n",
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type, expectedType));
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return FAIL;
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}
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return OK;
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@ -529,7 +525,7 @@ void setupDetector() {
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resetCore();
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//Initialization of acquistion parameters
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setTimer(SAMPLES_JCTB, DEFAULT_NUM_SAMPLES); // update databytes and allocate ram
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setTimer(SAMPLES, DEFAULT_NUM_SAMPLES); // update databytes and allocate ram
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setTimer(FRAME_NUMBER, DEFAULT_NUM_FRAMES);
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setTimer(CYCLES_NUMBER, DEFAULT_NUM_CYCLES);
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setTimer(FRAME_PERIOD, DEFAULT_PERIOD);
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@ -937,7 +933,7 @@ int64_t setTimer(enum timerIndex ind, int64_t val) {
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FILE_LOG(logDEBUG1, ("Getting #cycles: %lld\n", (long long int)retval));
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break;
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case SAMPLES_JCTB:
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case SAMPLES:
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if(val >= 0) {
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FILE_LOG(logINFO, ("Setting #samples: %lld\n", (long long int)val));
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nSamples = val;
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@ -10,12 +10,6 @@
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#define PROGRAMMING_MODE (0x2)
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#define CTRL_SRVR_INIT_TIME_US (300 * 1000)
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#ifdef JCTB
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#define DETNAME = "Jungfrau Chip Test Board";
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#else
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#define DETNAME = "Chip Test Board";
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#endif
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/* Struct Definitions */
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typedef struct ip_header_struct {
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uint16_t ip_len;
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@ -86,11 +80,7 @@ enum DACINDEX {D0, D1, D2, D3, D4, D5, D6, D7, D8, D9,
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#define VCHIP_POWER_INCRMNT (200)
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#define IP_PACKETSIZE (0x2032)
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#ifndef JCTB
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#define ADC_PORT_INVERT_VAL (0x453b2593)
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#else
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#define ADC_PORT_INVERT_VAL (0x453b2593)
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#endif
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#define MAXIMUM_ADC_CLK (40)
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#define PLL_VCO_FREQ_MHZ (400)
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@ -123,7 +123,7 @@ int LTC2620_VoltageToDac(int voltage, int* dacval) {
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* @returns FAIL when voltage outside limits, OK if conversion successful
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*/
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int LTC2620_DacToVoltage(int dacval, int* voltage) {
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return Common_VoltageToDac(dacval, voltage, LTC2620_MIN_MV, LTC2620_MaxMV, LTC2620_MAX_STEPS);
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return Common_DacToVoltage(dacval, voltage, LTC2620_MIN_MV, LTC2620_MaxMV, LTC2620_MAX_STEPS);
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}
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/**
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@ -147,11 +147,11 @@ void LTC2620_Configure(){
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/**
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* Set Dac value (obtains dacaddr, command and ichip and calls LTC2620_Set)
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* Set Dac (obtains dacaddr, command and ichip and calls LTC2620_Set)
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* @param dacnum dac number
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* @param data dac value to set
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*/
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void LTC2620_SetDACValue (int dacnum, int data) {
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void LTC2620_SetDAC (int dacnum, int data) {
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FILE_LOG(logDEBUG1, ("\tSetting dac %d to %d\n", dacnum, data));
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// LTC2620 index
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int ichip = dacnum / LTC2620_NUMCHANNELS;
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@ -16,6 +16,8 @@ const enum detectorType myDetectorType = EIGER;
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const enum detectorType myDetectorType = JUNGFRAU;
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#elif CHIPTESTBOARDD
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const enum detectorType myDetectorType = CHIPTESTBOARD;
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#elif MOENCHD
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const enum detectorType myDetectorType = MOENCH;
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#else
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const enum detectorType myDetectorType = GENERIC;
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#endif
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@ -33,7 +35,7 @@ extern char mess[MAX_STR_LENGTH];
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// Variables that will be exported
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int sockfd = 0;
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int debugflag = 0;
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#ifdef CHIPTESTBOARDD
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#if defined(CHIPTESTBOARDD) || defined(MOENCHD)
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int dataBytes = 0;
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uint16_t *ramValues = 0;
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int nframes = 0;
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@ -131,7 +133,7 @@ const char* getTimerName(enum timerIndex ind) {
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case MEASUREMENTS_NUMBER: return "measurements_number";
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case FRAMES_FROM_START: return "frames_from_start";
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case FRAMES_FROM_START_PG: return "frames_from_start_pg";
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case SAMPLES_JCTB: return "samples_jctb";
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case SAMPLES: return "samples";
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case SUBFRAME_ACQUISITION_TIME: return "subframe_acquisition_time";
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case SUBFRAME_DEADTIME: return "subframe_deadtime";
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case STORAGE_CELL_NUMBER: return "storage_cell_number";
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@ -1509,7 +1511,7 @@ int set_timer(int file_des) {
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#endif
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case FRAME_PERIOD:
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case CYCLES_NUMBER:
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case SAMPLES_JCTB:
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case SAMPLES:
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#if defined(GOTTHARDD) || defined(JUNGFRAUD) || defined(CHIPTESTBOARDD)
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case DELAY_AFTER_TRIGGER:
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#endif
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@ -1568,7 +1570,7 @@ int set_timer(int file_des) {
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case STORAGE_CELL_NUMBER:
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validate64(tns, retval, vtimerName, DEC); // no conversion, so all good
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break;
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case SAMPLES_JCTB:
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case SAMPLES:
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if (retval == -1) {
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ret = FAIL;
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retval = setTimer(ind, -1);
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