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some changes for chiptest board and mythen server now compiles

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This commit is contained in:
bergamaschi 2017-02-23 12:05:34 +01:00
parent 987aeda6fb
commit f12df80c5b
10 changed files with 328 additions and 368 deletions
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3
slsDetectorSoftware/commonFiles/sls_detector_defs.h
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@ -464,7 +464,8 @@ enum readOutFlags {
NONPARALLEL=0x20000,/**< eiger serial mode */ NONPARALLEL=0x20000,/**< eiger serial mode */
SAFE=0x40000/**< eiger safe mode */, SAFE=0x40000/**< eiger safe mode */,
DIGITAL_ONLY=0x80000, /** chiptest board read only digital bits (not adc values)*/ DIGITAL_ONLY=0x80000, /** chiptest board read only digital bits (not adc values)*/
ANALOG_AND_DIGITAL=0x100000 /** chiptest board read adc values and digital bits digital bits */ ANALOG_AND_DIGITAL=0x100000, /** chiptest board read adc values and digital bits digital bits */
DUT_CLK=0x200000, /** chiptest board fifo clock comes from device under test */
}; };
/** /**
trimming modes trimming modes

521
slsDetectorSoftware/jctbDetectorServer/firmware_funcs.c
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@ -99,12 +99,13 @@ int phase_shift=0;//DEFAULT_PHASE_SHIFT;
int ipPacketSize=DEFAULT_IP_PACKETSIZE; int ipPacketSize=DEFAULT_IP_PACKETSIZE;
int udpPacketSize=DEFAULT_UDP_PACKETSIZE; int udpPacketSize=DEFAULT_UDP_PACKETSIZE;
#ifndef NEW_PLL_RECONFIG #ifndef NEW_PLL_RECONFIG
u_int32_t clkDivider[2]={32,16}; u_int32_t clkDivider[4]={32,16,16,16};
#else #else
u_int32_t clkDivider[2]={40,20}; u_int32_t clkDivider[4]={40,20,20,200};
#endif #endif
int32_t clkPhase[2]={0,0}; int32_t clkPhase[4]={0,0,0,0};
u_int32_t adcDisableMask=0; u_int32_t adcDisableMask=0;
@ -226,32 +227,6 @@ u_int32_t bus_r(u_int32_t offset) {
} }
int setPhaseShiftOnce(){
u_int32_t addr, reg;
int i;
addr=MULTI_PURPOSE_REG;
reg=bus_r(addr);
#ifdef VERBOSE
printf("Multipurpose reg:%x\n",reg);
#endif
//Checking if it is power on(negative number)
// if(((reg&0xFFFF0000)>>16)>0){
//bus_w(addr,0x0); //clear the reg
if(reg==0){
printf("\nImplementing phase shift of %d\n",phase_shift);
for (i=1;i<phase_shift;i++) {
bus_w(addr,(INT_RSTN_BIT|ENET_RESETN_BIT|SW1_BIT|PHASE_STEP_BIT));//0x2821
bus_w(addr,(INT_RSTN_BIT|ENET_RESETN_BIT|(SW1_BIT&~PHASE_STEP_BIT)));//0x2820
}
#ifdef VERBOSE
printf("Multipupose reg now:%x\n",bus_r(addr));
#endif
}
return OK;
}
int cleanFifo(){ int cleanFifo(){
@ -343,7 +318,7 @@ u_int32_t putout(char *s, int modnum) {
//addr=DAC_REG+(modnum<<4); //addr=DAC_REG+(modnum<<4);
addr=DAC_REG;//+(modnum<<SHIFTMOD); commented by dhanya addr=DAC_REG;//+(modnum<<SHIFTMOD); commented by dhanya
bus_w(addr, pat); bus_w(addr, pat);
printf("ACHTUNG!!!!!!!!!!!!! Writing to DAc reg using putout!!!!!!!!!!!!!!!\n");
return OK; return OK;
} }
@ -440,197 +415,111 @@ void resetPLL() {
bus_w(PLL_CNTRL_REG, 0); bus_w(PLL_CNTRL_REG, 0);
} }
void configurePll(int i) { int configurePhase(int val, int i) {
u_int32_t l=0x0c; u_int32_t l=0x0c;
u_int32_t h=0x0d; u_int32_t h=0x0d;
u_int32_t val; u_int32_t vv;
int32_t phase=0, inv=0;
u_int32_t tot;
u_int32_t odd=1;//0;
if (i<0 || i>3)
return -1;
if (val>65535 || val<-65535)
return clkPhase[i];
// printf("PLL reconfig reset\N"); bus_w(PLL_CNTRL_REG,(1<<PLL_CNTR_RECONFIG_RESET_BIT)); usleep(100); bus_w(PLL_CNTRL_REG, 0);
bus_w(PLL_CNTRL_REG,((1<<PLL_CNTR_PLL_RESET_BIT))); //reset PLL
usleep(100);
bus_w(PLL_CNTRL_REG, 0);
setPllReconfigReg(PLL_MODE_REG,1,0);
printf("phase in %d\n",clkPhase[1]);
if (val>0) {
inv=0;
phase=val&0xffff;
} else {
inv=0;
val=-1*val;
phase=(~val)&0xffff;
}
vv=phase | (i<<16);// | (inv<<21);
setPllReconfigReg(PLL_PHASE_SHIFT_REG,vv,0);
clkPhase[i]=val;
return clkPhase[i];
}
int configureFrequency(int val, int i) {
u_int32_t l=0x0c;
u_int32_t h=0x0d;
u_int32_t vv;
int32_t phase=0, inv=0; int32_t phase=0, inv=0;
u_int32_t tot; u_int32_t tot;
u_int32_t odd=1;//0; u_int32_t odd=1;//0;
// printf("PLL reconfig reset\N"); bus_w(PLL_CNTRL_REG,(1<<PLL_CNTR_RECONFIG_RESET_BIT)); usleep(100); bus_w(PLL_CNTRL_REG, 0); // printf("PLL reconfig reset\N"); bus_w(PLL_CNTRL_REG,(1<<PLL_CNTR_RECONFIG_RESET_BIT)); usleep(100); bus_w(PLL_CNTRL_REG, 0);
if (i<0 || i>3)
#ifndef NEW_PLL_RECONFIG return -1;
printf("PLL mode\n"); setPllReconfigReg(PLL_MODE_REG,1,0);
// usleep(10000);
#endif
if (i<2) {
tot= PLL_VCO_FREQ_MHZ/clkDivider[i];
l=tot/2;
h=l;
if (tot>2*l) {
h=l+1;
odd=1;
}
printf("Counter %d: Low is %d, High is %d\n",i, l,h);
val= (i<<18)| (odd<<17) | l | (h<<8);
printf("Counter %d, val: %08x\n", i, val);
setPllReconfigReg(PLL_C_COUNTER_REG, val,0);
// usleep(20);
//change sync at the same time as
if (i>0) {
val= (2<<18)| (odd<<17) | l | (h<<8);
printf("Counter %d, val: %08x\n", i, val);
setPllReconfigReg(PLL_C_COUNTER_REG, val,0);
}
} else {
// if (mode==1) {
// } else {
printf("phase in %d\n",clkPhase[1]);
if (clkPhase[1]>0) {
inv=0;
phase=clkPhase[1];
} else {
inv=1;
phase=-1*clkPhase[1];
}
printf("phase out %d %08x\n",phase,phase);
if (inv) {
val=phase | (1<<16);// | (inv<<21);
printf("**************** phase word %08x\n",val);
// printf("Phase, val: %08x\n", val);
setPllReconfigReg(PLL_PHASE_SHIFT_REG,val,0); //shifts counter 0
} else {
val=phase ;// | (inv<<21);
printf("**************** phase word %08x\n",val);
// printf("Phase, val: %08x\n", val);
setPllReconfigReg(PLL_PHASE_SHIFT_REG,val,0); //shifts counter 0
#ifndef NEW_PLL_RECONFIG
printf("Start reconfig\n"); setPllReconfigReg(PLL_START_REG, 1,0);
// bus_w(PLL_CNTRL_REG, 0);
printf("Status register\n"); getPllReconfigReg(PLL_STATUS_REG,0);
// sleep(1);
printf("PLL mode\n"); setPllReconfigReg(PLL_MODE_REG,1,0); if (val<=0)
// usleep(10000); return clkDivider[i];
#endif if (i==1 || i==2){
printf("**************** phase word %08x\n",val); if (val>40) printf("Too high frequency %d MHz for these ADCs!\n", val);
val=phase | (2<<16);// | (inv<<21);
// printf("Phase, val: %08x\n", val);
setPllReconfigReg(PLL_PHASE_SHIFT_REG,val,0); //shifts counter 0
} }
tot= PLL_VCO_FREQ_MHZ/val;
} l=tot/2;
h=l;
#ifndef NEW_PLL_RECONFIG if (tot>2*l) {
printf("Start reconfig\n"); setPllReconfigReg(PLL_START_REG, 1,0); h=l+1;
odd=1;
// bus_w(PLL_CNTRL_REG, 0);
printf("Status register\n"); getPllReconfigReg(PLL_STATUS_REG,0);
// sleep(1);
#endif
// printf("PLL mode\n"); setPllReconfigReg(PLL_MODE_REG,0,0);
usleep(10000);
if (i<2) {
printf("reset pll\n");
bus_w(PLL_CNTRL_REG,((1<<PLL_CNTR_PLL_RESET_BIT))); //reset PLL
usleep(100);
bus_w(PLL_CNTRL_REG, 0);
} }
} else
{
odd=0;
}
printf("Counter %d: Low is %d, High is %d\n",i, l,h);
u_int32_t setClockDivider(int d, int ic) {
//u_int32_t l=0x0c;
//u_int32_t h=0x0d;
u_int32_t tot= PLL_VCO_FREQ_MHZ/d;
// int ic=0 is run clk; ic=1 is adc clk
printf("set clk divider %d to %d\n", ic, d);
if (ic>2)
return -1;
if (ic==2) {
printf("dbit clock is the same as adc clk\n");
ic=1;
}
if (ic==1 && d>40)
return -1;
if (d>160)
return -1;
if (tot>510)
return -1;
if (tot<1)
return -1;
clkDivider[ic]=d;
configurePll(ic);
return clkDivider[ic]; vv= (i<<18)| (odd<<17) | l | (h<<8);
}
int phaseStep(int st){
if (st>65535 || st<-65535) printf("Counter %d, val: %08x\n", i, vv);
return clkPhase[0]; setPllReconfigReg(PLL_C_COUNTER_REG, vv,0);
#ifdef NEW_PLL_RECONFIG /* // usleep(20); */
printf("reset pll\n"); /* //change sync at the same time as */
bus_w(PLL_CNTRL_REG,((1<<PLL_CNTR_PLL_RESET_BIT))); //reset PLL /* if (i>0) { */
usleep(100); /* val= (2<<18)| (odd<<17) | l | (h<<8); */
bus_w(PLL_CNTRL_REG, 0);
/* printf("Counter %d, val: %08x\n", i, val); */
/* setPllReconfigReg(PLL_C_COUNTER_REG, val,0); */
clkPhase[1]=st; /* } */
#else
clkPhase[1]=st-clkPhase[0];
#endif
printf("phase %d\n", clkPhase[1] );
configurePll(2);
clkPhase[0]=st;
return clkPhase[0]; usleep(10000);
}
printf("reset pll\n");
int dbitPhaseStep(int st){ bus_w(PLL_CNTRL_REG,((1<<PLL_CNTR_PLL_RESET_BIT))); //reset PLL
usleep(100);
printf("dbit clock is the same as adc clk\n"); bus_w(PLL_CNTRL_REG, 0);
return phaseStep(st);
return clkDivider[i];
} }
@ -639,63 +528,146 @@ int dbitPhaseStep(int st){
int getPhase() {
return clkPhase[0];
/* u_int32_t setClockDivider(int d, int ic) { */
};
/* //u_int32_t l=0x0c; */
/* //u_int32_t h=0x0d; */
/* u_int32_t tot= PLL_VCO_FREQ_MHZ/d; */
/* // int ic=0 is run clk; ic=1 is adc clk */
/* printf("set clk divider %d to %d\n", ic, d); */
/* if (ic>2) */
/* return -1; */
/* if (ic==2) { */
/* printf("dbit clock is the same as adc clk\n"); */
/* ic=1; */
/* } */
/* if (ic==1 && d>40) */
/* return -1; */
/* if (d>160) */
/* return -1; */
/* if (tot>510) */
/* return -1; */
/* if (tot<1) */
/* return -1; */
int getDbitPhase() { /* clkDivider[ic]=d; */
/* configurePll(ic); */
printf("dbit clock is the same as adc clk\n");
return getPhase(); /* return clkDivider[ic]; */
/* } */
/* int phaseStep(int st){ */
/* if (st>65535 || st<-65535) */
/* return clkPhase[0]; */
/* #ifdef NEW_PLL_RECONFIG */
/* printf("reset pll\n"); */
/* bus_w(PLL_CNTRL_REG,((1<<PLL_CNTR_PLL_RESET_BIT))); //reset PLL */
/* usleep(100); */
/* bus_w(PLL_CNTRL_REG, 0); */
}; /* clkPhase[1]=st; */
/* #else */
/* clkPhase[1]=st-clkPhase[0]; */
/* #endif */
/* printf("phase %d\n", clkPhase[1] ); */
/* configurePll(2); */
/* clkPhase[0]=st; */
/* return clkPhase[0]; */
/* } */
/* int dbitPhaseStep(int st){ */
/* printf("dbit clock is the same as adc clk\n"); */
/* return phaseStep(st); */
/* } */
u_int32_t getClockDivider(int ic) {
if (ic>2)
int getPhase(int i) {
if (i>=0 && i<4)
return clkPhase[i];
else
return -1; return -1;
if (ic==2) { };
printf("dbit clock is the same as adc clk\n");
ic=1;
}
return clkDivider[ic];
/* int getDbitPhase() { */
/* printf("dbit clock is the same as adc clk\n"); */
/* return getPhase(); */
/* }; */
/* u_int32_t getClockDivider(int ic) { */
/* if (ic>2) */
/* return -1; */
/* if (ic==2) { */
/* printf("dbit clock is the same as adc clk\n"); */
/* ic=1; */
/* } */
/* return clkDivider[ic]; */
/* int ic=0; */ /* /\* int ic=0; *\/ */
/* u_int32_t val; */ /* /\* u_int32_t val; *\/ */
/* u_int32_t l,h; */ /* /\* u_int32_t l,h; *\/ */
/* printf("get clk divider\n"); */ /* /\* printf("get clk divider\n"); *\/ */
/* setPllReconfigReg(PLL_MODE_REG,1,0); */ /* /\* setPllReconfigReg(PLL_MODE_REG,1,0); *\/ */
/* getPllReconfigReg(PLL_MODE_REG,0); */ /* /\* getPllReconfigReg(PLL_MODE_REG,0); *\/ */
/* u_int32_t addr=0xa; //c0 */ /* /\* u_int32_t addr=0xa; //c0 *\/ */
/* if (ic>0) */ /* /\* if (ic>0) *\/ */
/* addr=0xb; //c1 */ /* /\* addr=0xb; //c1 *\/ */
/* val=getPllReconfigReg(PLL_N_COUNTER_REG,0); */ /* /\* val=getPllReconfigReg(PLL_N_COUNTER_REG,0); *\/ */
/* printf("Getting N counter %08x\n",val); */ /* /\* printf("Getting N counter %08x\n",val); *\/ */
/* l=val&0xff; */ /* /\* l=val&0xff; *\/ */
/* h=(val>>8)&0xff; */ /* /\* h=(val>>8)&0xff; *\/ */
/* //getPllReconfigReg(PLL_STATUS_REG,0); */ /* /\* //getPllReconfigReg(PLL_STATUS_REG,0); *\/ */
/* val=getPllReconfigReg(addr,0); */ /* /\* val=getPllReconfigReg(addr,0); *\/ */
/* printf("Getting C counter %08x\n",val); */ /* /\* printf("Getting C counter %08x\n",val); *\/ */
/* return 800/(l+h); */ /* /\* return 800/(l+h); *\/ */
} /* } */
u_int32_t adcPipeline(int d) { u_int32_t adcPipeline(int d) {
@ -729,11 +701,11 @@ u_int32_t getSetLength() {
} }
u_int32_t setOversampling(int d) { u_int32_t setOversampling(int d) {
return 0;
/* if (d>=0 && d<=255) */
/* bus_w(OVERSAMPLING_REG, d); */
if (d>=0 && d<=255) /* return bus_r(OVERSAMPLING_REG); */
bus_w(OVERSAMPLING_REG, d);
return bus_r(OVERSAMPLING_REG);
} }
@ -746,23 +718,6 @@ u_int32_t getWaitStates() {
} }
u_int32_t setTotClockDivider(int d) {
return 0;
}
u_int32_t getTotClockDivider() {
return 0;
}
u_int32_t setTotDutyCycle(int d) {
return 0;
}
u_int32_t getTotDutyCycle() {
return 0;
}
u_int32_t setExtSignal(int d, enum externalSignalFlag mode) { u_int32_t setExtSignal(int d, enum externalSignalFlag mode) {
@ -1713,10 +1668,9 @@ int initHighVoltage(int val, int imod){
ddx=8; csdx=10; cdx=9; ddx=8; csdx=10; cdx=9;
codata=((dacvalue)&0xff); codata=((dacvalue)&0xff);
valw=bus_r(offw)&0x7fff; //switch off HV
valw=0xef|bus_r(offw); bus_w(offw,(valw)); // start point bus_w(offw,(valw)); // start point
valw=((valw&(~(0x1<<csdx))));bus_w(offw,valw); //chip sel bar down valw=((valw&(~(0x1<<csdx))));bus_w(offw,valw); //chip sel bar down
for (i=0;i<8;i++) { for (i=0;i<8;i++) {
valw=(valw&(~(0x1<<cdx)));bus_w(offw,valw); //cldwn valw=(valw&(~(0x1<<cdx)));bus_w(offw,valw); //cldwn
@ -1728,19 +1682,19 @@ int initHighVoltage(int val, int imod){
valw=(valw&(~(0x1<<cdx)));bus_w(offw,valw); //cldwn valw=(valw&(~(0x1<<cdx)));bus_w(offw,valw); //cldwn
valw=0xff|bus_r(offw); bus_w(offw,(valw)); // stop point =start point of course */ valw=0xff00|bus_r(offw); //switch on HV
bus_w(offw,(valw)); // stop point =start point of course */
printf("Writing %d in HVDAC \n",dacvalue); printf("Writing %d in HVDAC \n",dacvalue);
bus_w(HV_REG,val); bus_w(HV_REG,val);
} else { } else {
valw=bus_r(offw)&0xefff; valw=bus_r(offw)&0x7fff;
bus_w(offw,(valw)); bus_w(offw,(valw));
bus_w(HV_REG,0); bus_w(HV_REG,0);
} }
} }
@ -3568,28 +3522,28 @@ void initDac(int dacnum) {
printf("data bit=%d, clkbit=%d, csbit=%d",ddx,cdx,csdx); printf("data bit=%d, clkbit=%d, csbit=%d",ddx,cdx,csdx);
codata=(((0x6)<<4)|((0xf)<<16)|((0x0<<4)&0xfff0)); codata=(((0x6)<<4)|((0xf)<<16)|((0x0<<4)&0xfff0));
valw=0xffff; bus_w(offw,(valw)); // start point valw=0x00ff|(bus_r(offw)&0xff00);
valw=((valw&(~(0x1<<csdx))));bus_w(offw,valw); //chip sel bar down bus_w(offw,(valw)); // start point
for (i=1;i<25;i++) { valw=((valw&(~(0x1<<csdx))));bus_w(offw,valw); //chip sel bar down
for (i=1;i<25;i++) {
valw=(valw&(~(0x1<<cdx)));bus_w(offw,valw); //cldwn
valw=((valw&(~(0x1<<ddx)))+(((codata>>(24-i))&0x1)<<ddx));bus_w(offw,valw);//write data (i) valw=(valw&(~(0x1<<cdx)));bus_w(offw,valw); //cldwn
// printf("%d ", ((codata>>(24-i))&0x1)); valw=((valw&(~(0x1<<ddx)))+(((codata>>(24-i))&0x1)<<ddx));bus_w(offw,valw);//write data (i)
// printf("%d ", ((codata>>(24-i))&0x1));
valw=((valw&(~(0x1<<cdx)))+(0x1<<cdx));bus_w(offw,valw);//clkup
valw=((valw&(~(0x1<<cdx)))+(0x1<<cdx));bus_w(offw,valw);//clkup }
}
// printf("\n "); // printf("\n ");
valw=((valw&(~(0x1<<csdx)))+(0x1<<csdx));bus_w(offw,valw); //csup valw=((valw&(~(0x1<<csdx)))+(0x1<<csdx));bus_w(offw,valw); //csup
valw=(valw&(~(0x1<<cdx)));bus_w(offw,valw); //cldwn valw=(valw&(~(0x1<<cdx)));bus_w(offw,valw); //cldwn
valw=0xffff; bus_w(offw,(valw)); // stop point =start point of course */ valw=0x00ff|(bus_r(offw)&0xff00);
bus_w(offw,(valw)); // stop point =start point of course */
//end of setting int reference //end of setting int reference
@ -4002,7 +3956,9 @@ int setDac(int dacnum,int dacvalue){
offw=DAC_REG; offw=DAC_REG;
valw=bus_r(offw)|0xff; bus_w(offw,(valw)); // start point valw=bus_r(offw)|0xff;
bus_w(offw,(valw)); // start point
valw=((valw&(~(0x1<<csdx))));bus_w(offw,valw); //chip sel bar down valw=((valw&(~(0x1<<csdx))));bus_w(offw,valw); //chip sel bar down
valw=(valw&(~(0x1<<cdx)));bus_w(offw,valw); //cldwn valw=(valw&(~(0x1<<cdx)));bus_w(offw,valw); //cldwn
@ -4032,7 +3988,8 @@ int setDac(int dacnum,int dacvalue){
valw=(valw|(0x1<<csdx)); valw=(valw|(0x1<<csdx));
bus_w(offw,valw); //csup bus_w(offw,valw); //csup
valw=bus_r(offw)|0xff; bus_w(offw,(valw)); // stop point =start point of course */ valw=bus_r(offw)|0xff;
bus_w(offw,(valw)); // stop point =start point of course */
setDacRegister(dacnum,dacvalue); setDacRegister(dacnum,dacvalue);

24
slsDetectorSoftware/jctbDetectorServer/firmware_funcs.h
View File

@ -28,18 +28,20 @@ u_int16_t bus_w16(u_int32_t offset, u_int16_t data);//aldos function
u_int32_t bus_w(u_int32_t offset, u_int32_t data); u_int32_t bus_w(u_int32_t offset, u_int32_t data);
u_int32_t bus_r(u_int32_t offset); u_int32_t bus_r(u_int32_t offset);
int setPhaseShiftOnce(); //int setPhaseShiftOnce();
int phaseStep(int st); //int phaseStep(int st);
int dbitPhaseStep(int st); //int dbitPhaseStep(int st);
int getDbitPhase(); //int getDbitPhase();
int getPhase(); int getPhase(int i);
int cleanFifo(); int cleanFifo();
int setDAQRegister(); int setDAQRegister();
int configurePhase(int val, int i);
int configureFrequency(int val, int i);
u_int32_t putout(char *s, int modnum); u_int32_t putout(char *s, int modnum);
u_int32_t readin(int modnum); u_int32_t readin(int modnum);
u_int32_t setClockDivider(int d, int ic); //u_int32_t setClockDivider(int d, int ic);
u_int32_t getClockDivider(int ic); //u_int32_t getClockDivider(int ic);
void resetPLL(); void resetPLL();
u_int32_t setPllReconfigReg(u_int32_t reg, u_int32_t val, int trig); u_int32_t setPllReconfigReg(u_int32_t reg, u_int32_t val, int trig);
@ -49,10 +51,10 @@ u_int32_t setSetLength(int d);
u_int32_t getSetLength(); u_int32_t getSetLength();
u_int32_t setWaitStates(int d); u_int32_t setWaitStates(int d);
u_int32_t getWaitStates(); u_int32_t getWaitStates();
u_int32_t setTotClockDivider(int d); //u_int32_t setTotClockDivider(int d);
u_int32_t getTotClockDivider(); //u_int32_t getTotClockDivider();
u_int32_t setTotDutyCycle(int d); //u_int32_t setTotDutyCycle(int d);
u_int32_t getTotDutyCycle(); //u_int32_t getTotDutyCycle();
u_int32_t setOversampling(int d); u_int32_t setOversampling(int d);
u_int32_t adcPipeline(int d); u_int32_t adcPipeline(int d);
u_int32_t dbitPipeline(int d); u_int32_t dbitPipeline(int d);

BIN
slsDetectorSoftware/jctbDetectorServer/jungfrauDetectorServerTest
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Binary file not shown.

3
slsDetectorSoftware/jctbDetectorServer/registers_m.h
View File

@ -438,6 +438,9 @@
enum {run_clk_c, adc_clk_c, sync_clk_c, dbit_clk_c};
#define PLL_CNTR_ADDR_OFF 16 //PLL_CNTR_REG bits 21 downto 16 represent the counter address #define PLL_CNTR_ADDR_OFF 16 //PLL_CNTR_REG bits 21 downto 16 represent the counter address

89
slsDetectorSoftware/jctbDetectorServer/server_funcs.c
View File

@ -2488,17 +2488,17 @@ int set_speed(int file_des) {
if (ret==OK) { if (ret==OK) {
if (arg==PHASE_SHIFT || arg==ADC_PHASE) { /* if (arg==PHASE_SHIFT || arg==ADC_PHASE) { */
retval=phaseStep(val); /* retval=phaseStep(val); */
} else if ( arg==DBIT_PHASE) { /* } else if ( arg==DBIT_PHASE) { */
retval=dbitPhaseStep(val); /* retval=dbitPhaseStep(val); */
} else { /* } else { */
if (val!=-1) { /* if (val!=-1) { */
if (differentClients==1 && lockStatus==1 && val>=0) { if (differentClients==1 && lockStatus==1 && val>=0) {
@ -2506,8 +2506,23 @@ int set_speed(int file_des) {
sprintf(mess,"Detector locked by %s\n",lastClientIP); sprintf(mess,"Detector locked by %s\n",lastClientIP);
} else { } else {
switch (arg) { switch (arg) {
case PHASE_SHIFT:
case ADC_PHASE:
if (val==-1)
retval=getPhase(run_clk_c);
else
retval=configurePhase(val,run_clk_c);
break;
case DBIT_PHASE:
if (val==-1)
retval=getPhase(dbit_clk_c);
else
retval=configurePhase(val,dbit_clk_c);
break;
case CLOCK_DIVIDER: case CLOCK_DIVIDER:
retval=setClockDivider(val,0); retval=configureFrequency(val,run_clk_c);//setClockDivider(val,0);
break; break;
/* case PHASE_SHIFT: */ /* case PHASE_SHIFT: */
@ -2519,11 +2534,12 @@ int set_speed(int file_des) {
break; break;
case ADC_CLOCK: case ADC_CLOCK:
retval=setClockDivider(val,1); retval=configureFrequency(val,adc_clk_c);//setClockDivider(val,1);
configureFrequency(val,sync_clk_c);
break; break;
case DBIT_CLOCK: case DBIT_CLOCK:
retval=setClockDivider(val,2); retval=configureFrequency(val,dbit_clk_c);//setClockDivider(val,2);
break; break;
@ -2537,68 +2553,17 @@ int set_speed(int file_des) {
retval=dbitPipeline(val); retval=dbitPipeline(val);
break; break;
default: default:
ret=FAIL; ret=FAIL;
sprintf(mess,"Unknown speed parameter %d",arg); sprintf(mess,"Unknown speed parameter %d",arg);
} }
} }
} // }
}
switch (arg) {
case CLOCK_DIVIDER:
retval=getClockDivider(0);
break;
case PHASE_SHIFT:
retval=getPhase();
// retval=phaseStep(-1);
//ret=FAIL;
//sprintf(mess,"Cannot read phase",arg);
break;
case OVERSAMPLING:
retval=setOversampling(-1);
break;
case ADC_CLOCK:
retval=getClockDivider(1);
break;
case DBIT_CLOCK:
retval=getClockDivider(2);
break;
case ADC_PHASE:
retval=getPhase();
break;
case DBIT_PHASE:
retval=getDbitPhase();
break;
case ADC_PIPELINE:
retval=adcPipeline(-1);
break;
case DBIT_PIPELINE:
retval=dbitPipeline(-1);
break;
default:
ret=FAIL;
sprintf(mess,"Unknown speed parameter %d",arg);
}
} }
n = sendDataOnly(file_des,&ret,sizeof(ret)); n = sendDataOnly(file_des,&ret,sizeof(ret));

26
slsDetectorSoftware/mythenDetectorServer/mcb_funcs.c
View File

@ -63,15 +63,15 @@ int initDetector() {
detectorChans=malloc(n*NCHIP*NCHAN*sizeof(int)); detectorChans=malloc(n*NCHIP*NCHAN*sizeof(int));
detectorDacs=malloc(n*NDAC*sizeof(dacs_t)); detectorDacs=malloc(n*NDAC*sizeof(dacs_t));
detectorAdcs=malloc(n*NADC*sizeof(dacs_t)); detectorAdcs=malloc(n*NADC*sizeof(dacs_t));
#ifdef VERBOSE //#ifdef VERBOSE
printf("modules from 0x%x to 0x%x\n",detectorModules, detectorModules+n); printf("modules from 0x%x to 0x%x\n",detectorModules, detectorModules+n);
printf("chips from 0x%x to 0x%x\n",detectorChips, detectorChips+n*NCHIP); printf("chips from 0x%x to 0x%x\n",detectorChips, detectorChips+n*NCHIP);
printf("chans from 0x%x to 0x%x\n",detectorChans, detectorChans+n*NCHIP*NCHAN); printf("chans from 0x%x to 0x%x\n",detectorChans, detectorChans+n*NCHIP*NCHAN);
printf("dacs from 0x%x to 0x%x\n",detectorDacs, detectorDacs+n*NDAC); printf("dacs from 0x%x to 0x%x\n",detectorDacs, detectorDacs+n*NDAC);
printf("adcs from 0x%x to 0x%x\n",detectorAdcs, detectorAdcs+n*NADC); printf("adcs from 0x%x to 0x%x\n",detectorAdcs, detectorAdcs+n*NADC);
#endif //#endif
for (imod=0; imod<n; imod++) { for (imod=0; imod<n; imod++) {
printf("module %d\n",imod);
(detectorModules+imod)->dacs=detectorDacs+imod*NDAC; (detectorModules+imod)->dacs=detectorDacs+imod*NDAC;
(detectorModules+imod)->adcs=detectorAdcs+imod*NADC; (detectorModules+imod)->adcs=detectorAdcs+imod*NADC;
@ -87,6 +87,7 @@ int initDetector() {
(detectorModules+imod)->reg=0; (detectorModules+imod)->reg=0;
/* initialize registers, dacs, retrieve sn, adc values etc */ /* initialize registers, dacs, retrieve sn, adc values etc */
} }
printf("modules done\n");
thisSettings=UNINITIALIZED; thisSettings=UNINITIALIZED;
sChan=noneSelected; sChan=noneSelected;
sChip=noneSelected; sChip=noneSelected;
@ -99,9 +100,12 @@ int initDetector() {
clearSSregister(ALLMOD); clearSSregister(ALLMOD);
putout("0000000000000000",ALLMOD); putout("0000000000000000",ALLMOD);
printf("dr\n");
/* initialize dynamic range etc. */ /* initialize dynamic range etc. */
dynamicRange=getDynamicRange(); dynamicRange=getDynamicRange();
printf("nmod\n");
nModX=setNMod(-1); nModX=setNMod(-1);
printf("done\n");
@ -115,7 +119,7 @@ int initDetector() {
// allocateRAM(); // allocateRAM();
return OK; return OK;
} }
@ -919,6 +923,7 @@ int setSettings(int i) {
for (ind=0; ind<NDAC; ind++) for (ind=0; ind<NDAC; ind++)
v[ind]=-1; v[ind]=-1;
// printf("vind\n");
if (i!=GET_SETTINGS) { if (i!=GET_SETTINGS) {
switch (i) { switch (i) {
case STANDARD:; case FAST:; case HIGHGAIN: case STANDARD:; case FAST:; case HIGHGAIN:
@ -938,19 +943,20 @@ int setSettings(int i) {
irgpr=detectorDacs[4+imod*NDAC]; irgpr=detectorDacs[4+imod*NDAC];
irgsh1=detectorDacs[imod*NDAC+RGSH1]; irgsh1=detectorDacs[imod*NDAC+RGSH1];
irgsh2=detectorDacs[imod*NDAC+RGSH2]; irgsh2=detectorDacs[imod*NDAC+RGSH2];
*/
*/
// printf("regs\n");
irgpr=setDACRegister(RGPR,-1,imod); irgpr=setDACRegister(RGPR,-1,imod);
irgsh1=setDACRegister(RGSH1,-1,imod); irgsh1=setDACRegister(RGSH1,-1,imod);
irgsh2=setDACRegister(RGSH2,-1,imod); irgsh2=setDACRegister(RGSH2,-1,imod);
for (is=STANDARD; is<UNDEFINED; is++) { for (is=STANDARD; is<sizeof(rgpr); is++){//;UNDEFINED; is++) {
if (irgpr==rgpr[is] && irgsh1==rgsh1[is] && irgsh2==rgsh2[is]) { if (irgpr==rgpr[is] && irgsh1==rgsh1[is] && irgsh2==rgsh2[is]) {
isett=is; isett=is;
} }
} }
#ifdef VERBOSE //#ifdef VERBOSE
printf("Settings of module 0 are %d\n",isett); // printf("Settings of module 0 are %d\n",isett);
#endif //#endif
for (imod=1; imod<nModX; imod++) { for (imod=1; imod<nModX; imod++) {
if (isett!=UNDEFINED) { if (isett!=UNDEFINED) {
irgpr=setDACRegister(RGPR,-1,imod); irgpr=setDACRegister(RGPR,-1,imod);

BIN
slsDetectorSoftware/mythenDetectorServer/mythenDetectorServer
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6
slsDetectorSoftware/mythenDetectorServer/server_funcs.c
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@ -61,12 +61,18 @@ int init_detector( int b) {
if (b) { if (b) {
#ifdef MCB_FUNCS #ifdef MCB_FUNCS
initDetector(); initDetector();
printf("init \n");
setSettings(GET_SETTINGS); setSettings(GET_SETTINGS);
printf("get settings \n");
testRAM(); testRAM();
printf("test ram \n");
#endif #endif
setTiming(GET_EXTERNAL_COMMUNICATION_MODE); setTiming(GET_EXTERNAL_COMMUNICATION_MODE);
printf("timing \n");
setMaster(GET_MASTER); setMaster(GET_MASTER);
printf("master \n");
setSynchronization(GET_SYNCHRONIZATION_MODE); setSynchronization(GET_SYNCHRONIZATION_MODE);
printf("sync \n");
} }
strcpy(mess,"dummy message"); strcpy(mess,"dummy message");
strcpy(lastClientIP,"none"); strcpy(lastClientIP,"none");

24
slsDetectorSoftware/slsDetector/slsDetectorCommand.cpp
View File

@ -1144,6 +1144,11 @@ slsDetectorCommand::slsDetectorCommand(slsDetectorUtils *det) {
descrToFuncMap[i].m_pFuncPtr=&slsDetectorCommand::cmdPattern; descrToFuncMap[i].m_pFuncPtr=&slsDetectorCommand::cmdPattern;
i++; i++;
descrToFuncMap[i].m_pFuncName="dut_clk"; //
descrToFuncMap[i].m_pFuncPtr=&slsDetectorCommand::cmdPattern;
i++;
/* pulse */ /* pulse */
@ -4353,8 +4358,8 @@ string slsDetectorCommand::cmdSpeed(int narg, char *args[], int action) {
else if (cmd=="dbitphase") { else if (cmd=="dbitphase") {
index=DBIT_PHASE; index=DBIT_PHASE;
t=100000; t=100000;
} else if (cmd=="adcpipeline") } else if (cmd=="dbitpipeline")
index=ADC_PIPELINE; index=DBIT_PIPELINE;
else else
return string("could not decode speed variable ")+cmd; return string("could not decode speed variable ")+cmd;
@ -5273,6 +5278,21 @@ string slsDetectorCommand::cmdPattern(int narg, char *args[], int action) {
os << hex << myDet->readRegister(67) << dec; os << hex << myDet->readRegister(67) << dec;
} else if (cmd=="dut_clk") {
if (action==PUT_ACTION) {
if (sscanf(args[1],"%x",&addr))
;
else
return string("Could not scan dut_clk reg ")+string(args[1]);
myDet->writeRegister(123,addr); //0x7b
}
os << hex << myDet->readRegister(123) << dec; //0x7b
} else if (cmd=="adcdisable") { } else if (cmd=="adcdisable") {
int nroi=0; int nroi=0;