some changes for chiptest board and mythen server now compiles

This commit is contained in:
2017-02-23 12:05:34 +01:00
parent 987aeda6fb
commit f12df80c5b
10 changed files with 328 additions and 368 deletions

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@ -28,18 +28,20 @@ u_int16_t bus_w16(u_int32_t offset, u_int16_t data);//aldos function
u_int32_t bus_w(u_int32_t offset, u_int32_t data);
u_int32_t bus_r(u_int32_t offset);
int setPhaseShiftOnce();
int phaseStep(int st);
int dbitPhaseStep(int st);
int getDbitPhase();
int getPhase();
//int setPhaseShiftOnce();
//int phaseStep(int st);
//int dbitPhaseStep(int st);
//int getDbitPhase();
int getPhase(int i);
int cleanFifo();
int setDAQRegister();
int configurePhase(int val, int i);
int configureFrequency(int val, int i);
u_int32_t putout(char *s, int modnum);
u_int32_t readin(int modnum);
u_int32_t setClockDivider(int d, int ic);
u_int32_t getClockDivider(int ic);
//u_int32_t setClockDivider(int d, int ic);
//u_int32_t getClockDivider(int ic);
void resetPLL();
u_int32_t setPllReconfigReg(u_int32_t reg, u_int32_t val, int trig);
@ -49,10 +51,10 @@ u_int32_t setSetLength(int d);
u_int32_t getSetLength();
u_int32_t setWaitStates(int d);
u_int32_t getWaitStates();
u_int32_t setTotClockDivider(int d);
u_int32_t getTotClockDivider();
u_int32_t setTotDutyCycle(int d);
u_int32_t getTotDutyCycle();
//u_int32_t setTotClockDivider(int d);
//u_int32_t getTotClockDivider();
//u_int32_t setTotDutyCycle(int d);
//u_int32_t getTotDutyCycle();
u_int32_t setOversampling(int d);
u_int32_t adcPipeline(int d);
u_int32_t dbitPipeline(int d);