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This commit is contained in:
maliakal_d 2020-06-16 12:32:28 +02:00
parent c0e8e44b41
commit efc247f46f
5 changed files with 35 additions and 100 deletions
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4
slsDetectorGui/src/qDacWidget.cpp
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@ -45,7 +45,9 @@ void qDacWidget::GetDac() {
spinDac->setValue(retval); spinDac->setValue(retval);
// mv // mv
retval = det->getDAC(index, 1, {detectorIndex}).squash(-1); retval = det->getDAC(index, 1, {detectorIndex}).squash(-1);
lblDacmV->setText(QString("%1mV").arg(retval - 10)); // -6 is the minimum amt of space it occupies, if more needed, its
// padded with ' ', negative value for left aligned text
lblDacmV->setText(QString("%1mV").arg(retval, -6));
} }
CATCH_DISPLAY(std::string("Could not get dac ") + std::to_string(index), CATCH_DISPLAY(std::string("Could not get dac ") + std::to_string(index),
"qDacWidget::GetDac") "qDacWidget::GetDac")

77
slsDetectorServers/eigerDetectorServer/FebControl.c
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@ -12,8 +12,6 @@
#include <time.h> #include <time.h>
#include <unistd.h> #include <unistd.h>
// GetDAQStatusRegister(512,current_mode_bits_from_fpga)) {
char Module_dac_names[16][10] = {"VSvP", "Vtrim", "Vrpreamp", "Vrshaper", char Module_dac_names[16][10] = {"VSvP", "Vtrim", "Vrpreamp", "Vrshaper",
"VSvN", "Vtgstv", "Vcmp_ll", "Vcmp_lr", "VSvN", "Vtgstv", "Vcmp_ll", "Vcmp_lr",
"Vcal", "Vcmp_rl", "rxb_rb", "rxb_lb", "Vcal", "Vcmp_rl", "rxb_rb", "rxb_lb",
@ -27,7 +25,6 @@ int Feb_Control_normal = 0;
int Feb_Control_activated = 1; int Feb_Control_activated = 1;
int Feb_Control_hv_fd = -1; int Feb_Control_hv_fd = -1;
int Feb_Control_dacs[NDAC];
unsigned int Feb_Control_idelay[4]; // ll,lr,rl,ll unsigned int Feb_Control_idelay[4]; // ll,lr,rl,ll
int Feb_Control_counter_bit = 1; int Feb_Control_counter_bit = 1;
unsigned int Feb_Control_staticBits; unsigned int Feb_Control_staticBits;
@ -67,9 +64,6 @@ void Feb_Control_FebControl() {
int Feb_Control_Init(int master, int normal, int module_num) { int Feb_Control_Init(int master, int normal, int module_num) {
Feb_Control_master = master; Feb_Control_master = master;
Feb_Control_normal = normal; Feb_Control_normal = normal;
for (unsigned int i = 0; i < NDAC; ++i) {
Feb_Control_dacs[i] = 0;
}
Feb_Interface_SetAddress(Feb_Control_rightAddress, Feb_Control_leftAddress); Feb_Interface_SetAddress(Feb_Control_rightAddress, Feb_Control_leftAddress);
if (Feb_Control_activated) { if (Feb_Control_activated) {
return Feb_Interface_SetByteOrder(); return Feb_Interface_SetByteOrder();
@ -150,12 +144,6 @@ int Feb_Control_CheckSetup(int master) {
LOG(logERROR, ("high voltage not set.\n")); LOG(logERROR, ("high voltage not set.\n"));
return 0; return 0;
} }
for (unsigned int j = 0; j < NDAC; j++) {
if (Feb_Control_dacs[j] < 0) {
LOG(logERROR, ("\"%s\" dac is not set.\n", Module_dac_names[j]));
return 0;
}
}
LOG(logDEBUG1, ("Done Checking Set up\n")); LOG(logDEBUG1, ("Done Checking Set up\n"));
return 1; return 1;
} }
@ -517,69 +505,8 @@ float Feb_Control_DACToVoltage(unsigned int digital, unsigned int nsteps,
return vmin + (vmax - vmin) * digital / (nsteps - 1); return vmin + (vmax - vmin) * digital / (nsteps - 1);
} }
int Feb_Control_DecodeDACString(char *dac_str, unsigned int *dac_ch) { int Feb_Control_SetDAC(unsigned int dac_ch, int value) {
*dac_ch = 0; return Feb_Control_SendDACValue(Feb_Control_rightAddress, dac_ch, &value);
if (!Feb_Control_GetDACNumber(dac_str, dac_ch)) {
LOG(logERROR, ("invalid dac_name: %s \n", dac_str));
return 0;
}
return 1;
}
int Feb_Control_SetDAC(char *dac_str, int value, int is_a_voltage_mv) {
unsigned int dac_ch;
// test dac_ch validity
if (!Feb_Control_DecodeDACString(dac_str, &dac_ch))
return 0;
unsigned int v = value;
if (is_a_voltage_mv &&
!Feb_Control_VoltageToDAC(value, &v, 4096, 0, 2048)) {
LOG(logERROR,
("SetDac bad value, %d. The range is 0 to 2048 mV.\n", value));
return 0;
}
if (v < 0 || v > 4095) {
LOG(logERROR, ("SetDac bad value, %d. The range is 0 to 4095.\n", v));
return 0;
}
if (!Feb_Control_SendDACValue(Feb_Control_rightAddress, dac_ch, &v))
return 0;
Feb_Control_dacs[dac_ch] = v;
return 1;
}
int Feb_Control_GetDAC(char *s, int *ret_value, int voltage_mv) {
unsigned int dac_ch;
// test dac_ch validity
if (!Feb_Control_DecodeDACString(s, &dac_ch))
return 0;
*ret_value = Feb_Control_dacs[dac_ch];
if (voltage_mv)
*ret_value = Feb_Control_DACToVoltage(*ret_value, 4096, 0, 2048);
return 1;
}
int Feb_Control_GetDACName(unsigned int dac_num, char *s) {
if (dac_num >= NDAC) {
LOG(logERROR,
("GetDACName index out of range, %d invalid.\n", dac_num));
return 0;
}
strcpy(s, Module_dac_names[dac_num]);
return 1;
}
int Feb_Control_GetDACNumber(char *s, unsigned int *n) {
for (unsigned int i = 0; i < NDAC; i++) {
if (!strcmp(Module_dac_names[i], s)) {
*n = i;
return 1;
}
}
return 0;
} }
int Feb_Control_SendDACValue(unsigned int dst_num, unsigned int ch, int Feb_Control_SendDACValue(unsigned int dst_num, unsigned int ch,

6
slsDetectorServers/eigerDetectorServer/FebControl.h
View File

@ -31,11 +31,7 @@ int Feb_Control_VoltageToDAC(float value, unsigned int *digital,
unsigned int nsteps, float vmin, float vmax); unsigned int nsteps, float vmin, float vmax);
float Feb_Control_DACToVoltage(unsigned int digital, unsigned int nsteps, float Feb_Control_DACToVoltage(unsigned int digital, unsigned int nsteps,
float vmin, float vmax); float vmin, float vmax);
int Feb_Control_DecodeDACString(char *dac_str, unsigned int *dac_ch); int Feb_Control_SetDAC(unsigned int dac_ch, int value, );
int Feb_Control_SetDAC(char *s, int value, int is_a_voltage_mv);
int Feb_Control_GetDAC(char *s, int *ret_value, int voltage_mv);
int Feb_Control_GetDACName(unsigned int dac_num, char *s);
int Feb_Control_GetDACNumber(char *s, unsigned int *n);
int Feb_Control_SendDACValue(unsigned int dst_num, unsigned int ch, int Feb_Control_SendDACValue(unsigned int dst_num, unsigned int ch,
unsigned int *value); unsigned int *value);

24
slsDetectorServers/eigerDetectorServer/slsDetectorFunctionList.c
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@ -33,10 +33,6 @@ int initError = OK;
int initCheckDone = 0; int initCheckDone = 0;
char initErrorMessage[MAX_STR_LENGTH]; char initErrorMessage[MAX_STR_LENGTH];
const char *dac_names[16] = {"VSvP", "Vtrim", "Vrpreamp", "Vrshaper",
"VSvN", "Vtgstv", "Vcmp_ll", "Vcmp_lr",
"Vcal", "Vcmp_rl", "rxb_rb", "rxb_lb",
"Vcmp_rr", "Vcp", "Vcn", "Vishaper"};
int default_tau_from_file = -1; int default_tau_from_file = -1;
enum detectorSettings thisSettings; enum detectorSettings thisSettings;
sls_detector_module *detectorModules = NULL; sls_detector_module *detectorModules = NULL;
@ -1205,6 +1201,10 @@ void setDAC(enum DACINDEX ind, int val, int mV) {
return; return;
} }
char *dac_names[] = {DAC_NAMES};
LOG(logINFO, ("Setting dac[%d - %s]: %d %s \n", (int)ind, dac_names[ind],
val, (mV ? "mV" : "dac units")));
#ifdef VIRTUAL #ifdef VIRTUAL
int dacval = 0; int dacval = 0;
if (!mV) { if (!mV) {
@ -1216,11 +1216,17 @@ void setDAC(enum DACINDEX ind, int val, int mV) {
(detectorModules)->dacs[ind] = dacval; (detectorModules)->dacs[ind] = dacval;
} }
#else #else
char iname[10]; int dacval = val;
strcpy(iname, dac_names[(int)ind]); if (mV) {
if (Feb_Control_SetDAC(iname, val, mV)) { // convert to dac units
int dacval = 0; if (ConvertToDifferentRange(DAC_MIN_MV, DAC_MAX_MV, LTC2620_MIN_VAL,
Feb_Control_GetDAC(iname, &dacval, 0); LTC2620_MAX_VAL, val, &dacval) == FAIL) {
LOG(logERRROR,
("Could not convert %d mV for dac to dac units\n", val));
return;
}
}
if (Feb_Control_SetDAC(ind, dacval)) {
(detectorModules)->dacs[ind] = dacval; (detectorModules)->dacs[ind] = dacval;
} }
#endif #endif

24
slsDetectorServers/eigerDetectorServer/slsDetectorServer_defs.h
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@ -30,6 +30,10 @@ enum DACINDEX {
E_VISHAPER, E_VISHAPER,
E_VTHRESHOLD E_VTHRESHOLD
}; };
#define DAC_NAMES
"VSvP", "Vtrim", "Vrpreamp", "Vrshaper", "VSvN", "Vtgstv", "Vcmp_ll", "Vcmp_lr",
"Vcal", "Vcmp_rl", "rxb_rb", "rxb_lb", "Vcmp_rr", "Vcp", "Vcn",
"Vishaper"
#define DEFAULT_DAC_VALS \ #define DEFAULT_DAC_VALS \
{ \ { \
0, /* VSvP */ \ 0, /* VSvP */ \
@ -49,16 +53,16 @@ enum DACINDEX {
2000, /* Vcn */ \ 2000, /* Vcn */ \
1550 /* Vishaper */ \ 1550 /* Vishaper */ \
}; };
enum ADCINDEX { enum ADCINDEX {
TEMP_FPGAEXT, TEMP_FPGAEXT,
TEMP_10GE, TEMP_10GE,
TEMP_DCDC, TEMP_DCDC,
TEMP_SODL, TEMP_SODL,
TEMP_SODR, TEMP_SODR,
TEMP_FPGA, TEMP_FPGA,
TEMP_FPGAFEBL, TEMP_FPGAFEBL,
TEMP_FPGAFEBR TEMP_FPGAFEBR
}; };
enum NETWORKINDEX { TXN_LEFT, TXN_RIGHT, TXN_FRAME, FLOWCTRL_10G }; enum NETWORKINDEX { TXN_LEFT, TXN_RIGHT, TXN_FRAME, FLOWCTRL_10G };
enum ROINDEX { E_PARALLEL, E_NON_PARALLEL }; enum ROINDEX { E_PARALLEL, E_NON_PARALLEL };
enum CLKINDEX { RUN_CLK, NUM_CLOCKS }; enum CLKINDEX { RUN_CLK, NUM_CLOCKS };