eiger server fixes:

- removed feb reset in stop acquisition as it caused processing bit to randomly not go high (leads to infinite loop waiting for it to go high). This is anyway done at prepare acquisition and set trimbits.
- left AND right registers monitored for processing bit done
- febProcessinginprogress returns STATUS_IDLE and not IDLE
- In feb stop acquisition, if processing bit is running forever, checks for 1 s, then if acq done bit is high, returns ok, else throws
- feb stop acquisition returns 1 if success and fucntion in list calling it compares properly instead of STATUS_IDLE (no effect, but incorrect logic)
- chipsignals to trimquad should only monitor right fpga (not both as it will throw)
- fixed error messages of readregister inconsistent values
- setmodule and read frame was returning fail without setting error messages (leading to broken tcp connection due to no error message)
-

slsDetectorServers/slsDetectorServer/src/slsDetectorServer_funcs.c

@@ -1499,7 +1499,7 @@ int write_register(int file_des) {
         } else {
             if (readRegister(addr, &retval) == FAIL) {
                 ret = FAIL;
-                sprintf(mess, "Could not read register 0x%x.\n", addr);
+                sprintf(mess, "Could not read register 0x%x or inconsistent values. Try to read +0x100 for only left and +0x200 for only right.\n", addr);
                 LOG(logERROR, (mess));
             }
         }
@@ -1537,7 +1537,7 @@ int read_register(int file_des) {
 #elif EIGERD
     if (readRegister(addr, &retval) == FAIL) {
         ret = FAIL;
-        sprintf(mess, "Could not read register 0x%x.\n", addr);
+        sprintf(mess, "Could not read register 0x%x or inconsistent values. Try +0x100 for only left and +0x200 for only right..\n", addr);
         LOG(logERROR, (mess));
     }
 #else