eiger server fixes:

- removed feb reset in stop acquisition as it caused processing bit to randomly not go high (leads to infinite loop waiting for it to go high). This is anyway done at prepare acquisition and set trimbits.
- left AND right registers monitored for processing bit done
- febProcessinginprogress returns STATUS_IDLE and not IDLE
- In feb stop acquisition, if processing bit is running forever, checks for 1 s, then if acq done bit is high, returns ok, else throws
- feb stop acquisition returns 1 if success and fucntion in list calling it compares properly instead of STATUS_IDLE (no effect, but incorrect logic)
- chipsignals to trimquad should only monitor right fpga (not both as it will throw)
- fixed error messages of readregister inconsistent values
- setmodule and read frame was returning fail without setting error messages (leading to broken tcp connection due to no error message)
-

slsDetectorServers/eigerDetectorServer/FebControl.c

@@ -715,7 +715,7 @@ int Feb_Control_ProcessingInProgress() {
     unsigned int regr = 0, regl = 0;
     // deactivated should return end of processing
     if (!Feb_Control_activated)
-        return IDLE;
+        return STATUS_IDLE;
 
     if (!Feb_Interface_ReadRegister(Feb_Control_rightAddress, FEB_REG_STATUS,
                                     &regr)) {
@@ -729,8 +729,9 @@ int Feb_Control_ProcessingInProgress() {
                        "processing status\n"));
         return STATUS_ERROR;
     }
+    LOG(logDEBUG1, ("regl:0x%x regr:0x%x\n", regl, regr));
     // processing done
-    if ((regr | regl) & FEB_REG_STATUS_ACQ_DONE_MSK) {
+    if (regr & regl & FEB_REG_STATUS_ACQ_DONE_MSK) {
         return STATUS_IDLE;
     }
     // processing running
@@ -1046,6 +1047,7 @@ int Feb_Control_StopAcquisition() {
         // wait for feb processing to be done
         int is_processing = Feb_Control_ProcessingInProgress();
         int check_error = 0;
+        int check_stuck = 0;
         while (is_processing != STATUS_IDLE) {
             usleep(500);
             is_processing = Feb_Control_ProcessingInProgress();
@@ -1057,12 +1059,28 @@ int Feb_Control_StopAcquisition() {
                     break;
                 check_error++;
             } // reset check_error for next time
-            else
+            else {
                 check_error = 0;
+            }
+
+            // check stuck only 2000 times (1s)
+            if (is_processing == STATUS_RUNNING) {
+                if (check_stuck == 2000) {
+                    LOG(logERROR, ("Unable to get feb processing done signal\n"));
+                    // at least it is idle
+                    if (Feb_Control_AcquisitionInProgress() == STATUS_IDLE) {
+                       return 1;
+                    }
+                    LOG(logERROR, ("Unable to get acquisition done signal\n"));
+                    return 0;
+                }
+                check_stuck++;
+            } // reset check_stuck for next time
+            else {
+                check_stuck = 0;
+            }
         }
         LOG(logINFO, ("Feb: Processing done (to stop acq)\n"));
-
-        return 0;
     }
     return 1;
 }
@@ -1544,7 +1562,9 @@ int Feb_Control_SetChipSignalsToTrimQuad(int enable) {
         LOG(logINFO, ("%s chip signals to trim quad\n",
                       enable ? "Enabling" : "Disabling"));
         unsigned int regval = 0;
-        if (!Feb_Control_ReadRegister(DAQ_REG_HRDWRE, &regval)) {
+        // right fpga only
+        uint32_t righOffset = DAQ_REG_HRDWRE + Feb_Control_rightAddress;
+        if (!Feb_Control_ReadRegister(righOffset, &regval)) {
             LOG(logERROR, ("Could not set chip signals to trim quad\n"));
             return 0;
         }
@@ -1554,7 +1574,7 @@ int Feb_Control_SetChipSignalsToTrimQuad(int enable) {
             regval &= ~(DAQ_REG_HRDWRE_PROGRAM_MSK | DAQ_REG_HRDWRE_M8_MSK);
         }
 
-        return Feb_Control_WriteRegister(DAQ_REG_HRDWRE, regval);
+        return Feb_Control_WriteRegister(righOffset, regval);
     }
     return 1;
 }
@@ -1587,19 +1607,19 @@ int Feb_Control_WriteRegister(uint32_t offset, uint32_t data) {
 
     int run[2] = {0, 0};
     // both registers
-    if (offset < 0x100) {
+    if (offset < Feb_Control_leftAddress) {
         run[0] = 1;
         run[1] = 1;
     }
     // right registers only
-    else if (offset >= 0x200) {
+    else if (offset >= Feb_Control_rightAddress) {
         run[0] = 1;
-        actualOffset = offset - 0x200;
+        actualOffset = offset - Feb_Control_rightAddress;
     }
     // left registers only
     else {
         run[1] = 1;
-        actualOffset = offset - 0x100;
+        actualOffset = offset - Feb_Control_leftAddress;
     }
 
     for (int iloop = 0; iloop < 2; ++iloop) {
@@ -1625,19 +1645,19 @@ int Feb_Control_ReadRegister(uint32_t offset, uint32_t *retval) {
     uint32_t value[2] = {0, 0};
     int run[2] = {0, 0};
     // both registers
-    if (offset < 0x100) {
+    if (offset < Feb_Control_leftAddress) {
         run[0] = 1;
         run[1] = 1;
     }
     // right registers only
-    else if (offset >= 0x200) {
+    else if (offset >= Feb_Control_rightAddress) {
         run[0] = 1;
-        actualOffset = offset - 0x200;
+        actualOffset = offset - Feb_Control_rightAddress;
     }
     // left registers only
     else {
         run[1] = 1;
-        actualOffset = offset - 0x100;
+        actualOffset = offset - Feb_Control_leftAddress;
     }
 
     for (int iloop = 0; iloop < 2; ++iloop) {
@@ -1658,11 +1678,11 @@ int Feb_Control_ReadRegister(uint32_t offset, uint32_t *retval) {
             }
         }
     }
-    // Inconsistent values
-    if (value[0] != value[1]) {
+    // Inconsistent values when reading both registers
+    if ((run[0] & run[1]) & (value[0] != value[1])) {
         LOG(logERROR,
-            ("Inconsistent values read from left 0x%x and right 0x%x\n",
-             value[0], value[1]));
+            ("Inconsistent values read from %s 0x%x and %s 0x%x\n",
+             side[0], value[0], side[1], value[1]));
         return 0;
     }
     return 1;