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mythen3: txndelay frame added

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This commit is contained in:
maliakal_d
2020-08-18 15:27:30 +02:00
parent afabc9a503
commit eeb386fef5
8 changed files with 47 additions and 9 deletions
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7
slsDetectorServers/mythen3DetectorServer/RegisterDefs.h
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@ -140,6 +140,13 @@
#define DTA_OFFSET_REG (0x24 * REG_OFFSET + BASE_CONTROL)
/* Formatting for data core -----------------------------------------------*/
#define FMT_CONFIG_REG (0x00 * REG_OFFSET + BASE_FMT)
#define FMT_CONFIG_TXN_DELAY_OFST (0)
#define FMT_CONFIG_TXN_DELAY_MSK (0x00FFFFFF << FMT_CONFIG_TXN_DELAY_OFST)
/* Packetizer -------------------------------------------------------------*/
/* Packetizer Config Register */

22
slsDetectorServers/mythen3DetectorServer/slsDetectorFunctionList.c
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@ -2067,6 +2067,28 @@ int getClockDivider(enum CLKINDEX ind) {
return clkDivider[ind];
}
int getTransmissionDelayFrame() {
return ((bus_r(FMT_CONFIG_REG) & FMT_CONFIG_TXN_DELAY_MSK) >>
FMT_CONFIG_TXN_DELAY_OFST);
}
int setTransmissionDelayFrame(int value) {
if (value < 0 || value > MAX_TIMESLOT_VAL) {
LOG(logERROR, ("Transmission delay %d should be in range: 0 - %d\n",
value, MAX_TIMESLOT_VAL));
return FAIL;
}
LOG(logINFO, ("Setting transmission delay: %d\n", value));
uint32_t addr = FMT_CONFIG_REG;
bus_w(addr, bus_r(addr) & ~FMT_CONFIG_TXN_DELAY_MSK);
bus_w(addr, (bus_r(addr) | ((value << FMT_CONFIG_TXN_DELAY_OFST) &
FMT_CONFIG_TXN_DELAY_MSK)));
LOG(logDEBUG1, ("Transmission delay read %d\n",
((bus_r(addr) & FMT_CONFIG_TXN_DELAY_MSK) >>
FMT_CONFIG_TXN_DELAY_OFST)));
return OK;
}
/* aquisition */
int startStateMachine() {

1
slsDetectorServers/mythen3DetectorServer/slsDetectorServer_defs.h
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@ -45,6 +45,7 @@
#define DEFAULT_MSTR_OTPT_P1_NUM_PULSES (20)
/* Firmware Definitions */
#define MAX_TIMESLOT_VAL (0xFFFFFF)
#define IP_HEADER_SIZE (20)
#define FIXED_PLL_FREQUENCY (020000000) // 20MHz
#define READOUT_PLL_VCO_FREQ_HZ (1250000000) // 1.25GHz