detectors/slsDetectorPackage
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ctb, moench, jungfrau server: changing phase only changes one clock in one direction. ctb and moench phase shift connected to adc clk, instead of run clk

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This commit is contained in:
maliakal_d
2019-03-13 08:37:45 +01:00
parent 6765fd0dc8
commit ec18db868f
12 changed files with 77 additions and 64 deletions
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12
slsDetectorServers/moenchDetectorServer/gitInfo.txt
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@ -1,9 +1,9 @@
Path: slsDetectorPackage/slsDetectorServers/moenchDetectorServer
URL: origin git@github.com:slsdetectorgroup/slsDetectorPackage.git
Repository Root: origin git@github.com:slsdetectorgroup/slsDetectorPackage.git
Repsitory UUID: ae5938799fb1bf7a5cb64bdb329f9c0d9ab44a03
Revision: 15
URL: origin https://www.github.com/slsdetectorgroup/slsDetectorPackage
Repository Root: origin https://www.github.com/slsdetectorgroup/slsDetectorPackage
Repsitory UUID: 6765fd0dc89176b4eceaf5e2304ef808a316ba9b
Revision: 16
Branch: refactor
Last Changed Author: Dhanya_Thattil
Last Changed Rev: 4393
Last Changed Date: 2019-03-08 14:05:26.000000002 +0100 ./RegisterDefs.h
Last Changed Rev: 4394
Last Changed Date: 2019-03-13 08:04:56.000000002 +0100 ./RegisterDefs.h

8
slsDetectorServers/moenchDetectorServer/gitInfoMoench.h
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@ -1,6 +1,6 @@
#define GITURL "git@github.com:slsdetectorgroup/slsDetectorPackage.git"
#define GITREPUUID "ae5938799fb1bf7a5cb64bdb329f9c0d9ab44a03"
#define GITURL "https://www.github.com/slsdetectorgroup/slsDetectorPackage"
#define GITREPUUID "6765fd0dc89176b4eceaf5e2304ef808a316ba9b"
#define GITAUTH "Dhanya_Thattil"
#define GITREV 0x4393
#define GITDATE 0x20190308
#define GITREV 0x4394
#define GITDATE 0x20190313
#define GITBRANCH "refactor"

25
slsDetectorServers/moenchDetectorServer/slsDetectorFunctionList.c
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@ -762,7 +762,7 @@ void setSpeed(enum speedVariable ind, int val) {
case ADC_PHASE:
case PHASE_SHIFT:
FILE_LOG(logINFOBLUE, ("Configuring ADC Phase\n"));
configurePhase(RUN_CLK, val);
configurePhase(ADC_CLK, val);
break;
case DBIT_PHASE:
FILE_LOG(logINFOBLUE, ("Configuring Dbit Phase\n"));
@ -1274,6 +1274,12 @@ void configurePhase(enum CLKINDEX ind, int val) {
FILE_LOG(logERROR, ("\tPhase provided for C%d(%s) outside limits\n", ind, clock_names[ind]));
return;
}
int relativePhase = clkPhase[ind] - val;
// same phase
if (!relativePhase) {
return;
}
FILE_LOG(logINFO, ("Configuring Phase of C%d(%s) to %d\n", ind, clock_names[ind], val));
@ -1283,16 +1289,17 @@ void configurePhase(enum CLKINDEX ind, int val) {
// set mode register to polling mode
ALTERA_PLL_SetModePolling();
int phase = 0, inv = 0;
if (val > 0) {
inv = 0;
phase = val;
int phase = 0;
int maxShifts = ((ind == ADC_CLK) ? MAX_PHASE_SHIFTS_ADC_CLK : MAX_PHASE_SHIFTS_DBIT_CLK);
// delay clk
if (relativePhase > 0) {
phase = (maxShifts - relativePhase);
} else {
inv = 1;
val = -1 * val;
phase = (~val);
phase = (-1) * relativePhase;
}
FILE_LOG(logINFO, ("\tphase out %d (0x%08x), inv:%d\n", phase, phase, inv));
FILE_LOG(logINFO, ("\tphase out %d (0x%08x)\n", phase, phase));
ALTERA_PLL_SetPhaseShift(phase, (int)ind, 0);

3
slsDetectorServers/moenchDetectorServer/slsDetectorServer_defs.h
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@ -61,7 +61,8 @@ enum DACINDEX {D0, D1, D2, D3, D4, D5, D6, D7};
/* Defines in the Firmware */
#define MAX_PATTERN_LENGTH (0xFFFF)
#define DIGITAL_IO_DELAY_MAXIMUM_PS ((OUTPUT_DELAY_0_OTPT_STTNG_MSK >> OUTPUT_DELAY_0_OTPT_STTNG_OFST) * OUTPUT_DELAY_0_OTPT_STTNG_STEPS)
#define MAX_PHASE_SHIFTS_ADC_CLK (320)
#define MAX_PHASE_SHIFTS_DBIT_CLK (32)
#define WAIT_TME_US_FR_ACQDONE_REG (100) // wait time in us after acquisition done to ensure there is no data in fifo
#define WAIT_TIME_US_PLL (10 * 1000)