mirror of
https://github.com/slsdetectorgroup/slsDetectorPackage.git
synced 2025-06-24 02:27:59 +02:00
ctb, moench, jungfrau server: changing phase only changes one clock in one direction. ctb and moench phase shift connected to adc clk, instead of run clk
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@ -1,9 +1,9 @@
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Path: slsDetectorPackage/slsDetectorServers/jungfrauDetectorServer
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URL: origin git@github.com:slsdetectorgroup/slsDetectorPackage.git
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Repository Root: origin git@github.com:slsdetectorgroup/slsDetectorPackage.git
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Repsitory UUID: 93192c6e84a34ad3416f99b95e58356b609f61c6
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Revision: 24
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URL: origin https://www.github.com/slsdetectorgroup/slsDetectorPackage
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Repository Root: origin https://www.github.com/slsdetectorgroup/slsDetectorPackage
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Repsitory UUID: 6765fd0dc89176b4eceaf5e2304ef808a316ba9b
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Revision: 26
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Branch: refactor
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Last Changed Author: Dhanya_Thattil
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Last Changed Rev: 4370
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Last Changed Date: 2019-03-01 15:23:53.000000002 +0100 ./RegisterDefs.h
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Last Changed Rev: 4394
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Last Changed Date: 2019-03-13 08:04:56.000000002 +0100 ./RegisterDefs.h
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@ -1,6 +1,6 @@
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#define GITURL "git@github.com:slsdetectorgroup/slsDetectorPackage.git"
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#define GITREPUUID "93192c6e84a34ad3416f99b95e58356b609f61c6"
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#define GITURL "https://www.github.com/slsdetectorgroup/slsDetectorPackage"
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#define GITREPUUID "6765fd0dc89176b4eceaf5e2304ef808a316ba9b"
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#define GITAUTH "Dhanya_Thattil"
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#define GITREV 0x4370
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#define GITDATE 0x20190301
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#define GITREV 0x4394
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#define GITDATE 0x20190313
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#define GITBRANCH "refactor"
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@ -1255,29 +1255,25 @@ void configurePll() {
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#ifdef VIRTUAL
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return;
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#endif
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int32_t phase=0, inv=0;
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int32_t phase=0;
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// ensuring PLL is never configured with same phase
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if (clkPhase[1] == 0) {
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return;
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}
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FILE_LOG(logINFO, ("\tConfiguring PLL with phase in %d\n", clkPhase[1]));
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// delay ADC clk
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if (clkPhase[1]>0) {
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inv=0;
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phase=clkPhase[1];
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} else {
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inv=1;
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phase=-1*clkPhase[1];
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phase = MAX_PHASE_SHIFTS - clkPhase[1];
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}
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// advance adc clk
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else {
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phase = (-1) * clkPhase[1];
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}
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FILE_LOG(logDEBUG1, ("\tphase out %d (0x%08x)\n", phase, phase));
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if (inv) {
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ALTERA_PLL_SetPhaseShift(phase, 1, 0);
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} else {
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ALTERA_PLL_SetPhaseShift(phase, 0, 0);
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ALTERA_PLL_SetPhaseShift(phase, 2, 0);
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}
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ALTERA_PLL_SetPhaseShift(phase, 1, 0); // phase, 1: adc clk, 0:neg
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usleep(10000);
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}
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@ -88,6 +88,7 @@ enum NETWORKINDEX { TXN_FRAME };
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#define ADC_PHASE_HALF_SPEED (0x2D) //45
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#define ADC_PHASE_QUARTER_SPEED (0x2D) //45
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#define ADC_PORT_INVERT_VAL (0x453b2a9c)
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#define MAX_PHASE_SHIFTS (160)
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/* MSB & LSB DEFINES */
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#define MSB_OF_64_BIT_REG_OFST (32)
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