ctb, moench, jungfrau server: changing phase only changes one clock in one direction. ctb and moench phase shift connected to adc clk, instead of run clk

This commit is contained in:
2019-03-13 08:37:45 +01:00
parent 6765fd0dc8
commit ec18db868f
12 changed files with 77 additions and 64 deletions

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@ -1,9 +1,9 @@
Path: slsDetectorPackage/slsDetectorServers/jungfrauDetectorServer
URL: origin git@github.com:slsdetectorgroup/slsDetectorPackage.git
Repository Root: origin git@github.com:slsdetectorgroup/slsDetectorPackage.git
Repsitory UUID: 93192c6e84a34ad3416f99b95e58356b609f61c6
Revision: 24
URL: origin https://www.github.com/slsdetectorgroup/slsDetectorPackage
Repository Root: origin https://www.github.com/slsdetectorgroup/slsDetectorPackage
Repsitory UUID: 6765fd0dc89176b4eceaf5e2304ef808a316ba9b
Revision: 26
Branch: refactor
Last Changed Author: Dhanya_Thattil
Last Changed Rev: 4370
Last Changed Date: 2019-03-01 15:23:53.000000002 +0100 ./RegisterDefs.h
Last Changed Rev: 4394
Last Changed Date: 2019-03-13 08:04:56.000000002 +0100 ./RegisterDefs.h

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@ -1,6 +1,6 @@
#define GITURL "git@github.com:slsdetectorgroup/slsDetectorPackage.git"
#define GITREPUUID "93192c6e84a34ad3416f99b95e58356b609f61c6"
#define GITURL "https://www.github.com/slsdetectorgroup/slsDetectorPackage"
#define GITREPUUID "6765fd0dc89176b4eceaf5e2304ef808a316ba9b"
#define GITAUTH "Dhanya_Thattil"
#define GITREV 0x4370
#define GITDATE 0x20190301
#define GITREV 0x4394
#define GITDATE 0x20190313
#define GITBRANCH "refactor"

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@ -1255,29 +1255,25 @@ void configurePll() {
#ifdef VIRTUAL
return;
#endif
int32_t phase=0, inv=0;
int32_t phase=0;
// ensuring PLL is never configured with same phase
if (clkPhase[1] == 0) {
return;
}
FILE_LOG(logINFO, ("\tConfiguring PLL with phase in %d\n", clkPhase[1]));
// delay ADC clk
if (clkPhase[1]>0) {
inv=0;
phase=clkPhase[1];
} else {
inv=1;
phase=-1*clkPhase[1];
phase = MAX_PHASE_SHIFTS - clkPhase[1];
}
// advance adc clk
else {
phase = (-1) * clkPhase[1];
}
FILE_LOG(logDEBUG1, ("\tphase out %d (0x%08x)\n", phase, phase));
if (inv) {
ALTERA_PLL_SetPhaseShift(phase, 1, 0);
} else {
ALTERA_PLL_SetPhaseShift(phase, 0, 0);
ALTERA_PLL_SetPhaseShift(phase, 2, 0);
}
ALTERA_PLL_SetPhaseShift(phase, 1, 0); // phase, 1: adc clk, 0:neg
usleep(10000);
}

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@ -88,6 +88,7 @@ enum NETWORKINDEX { TXN_FRAME };
#define ADC_PHASE_HALF_SPEED (0x2D) //45
#define ADC_PHASE_QUARTER_SPEED (0x2D) //45
#define ADC_PORT_INVERT_VAL (0x453b2a9c)
#define MAX_PHASE_SHIFTS (160)
/* MSB & LSB DEFINES */
#define MSB_OF_64_BIT_REG_OFST (32)