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maliakal_d 2025-01-31 12:27:35 +01:00
parent 0e45ae189d
commit e92578f89d
13 changed files with 135 additions and 126 deletions
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4
slsDetectorGui/include/qDefs.h
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@ -61,7 +61,9 @@ class qDefs : public QWidget {
} }
} }
template <class CT> struct NonDeduced { using type = CT; }; template <class CT> struct NonDeduced {
using type = CT;
};
template <class S, typename RT, typename... CT> template <class S, typename RT, typename... CT>
static void HandleExceptions(const std::string emsg, const std::string src, static void HandleExceptions(const std::string emsg, const std::string src,
S *s, RT (S::*somefunc)(CT...), S *s, RT (S::*somefunc)(CT...),

2
slsDetectorServers/eigerDetectorServer/9mhvserial_bf.c
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@ -17,7 +17,7 @@
#define BUFFERSIZE 16 #define BUFFERSIZE 16
#define I2C_DEVICE_FILE "/dev/i2c-0" #define I2C_DEVICE_FILE "/dev/i2c-0"
#define I2C_DEVICE_ADDRESS 0x4C #define I2C_DEVICE_ADDRESS 0x4C
//#define I2C_DEVICE_ADDRESS 0x48 // #define I2C_DEVICE_ADDRESS 0x48
#define I2C_REGISTER_ADDRESS 0x40 #define I2C_REGISTER_ADDRESS 0x40
int i2c_open(const char *file, unsigned int addr) { int i2c_open(const char *file, unsigned int addr) {

5
slsDetectorServers/eigerDetectorServer/FebRegisterDefs.h
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@ -98,7 +98,7 @@
// everything at ~200 kHz (200 kHz MHz ddr readout) // everything at ~200 kHz (200 kHz MHz ddr readout)
#define DAQ_CHIP_CONTROLLER_SUPER_SLOW_SPEED 0x000c0000 #define DAQ_CHIP_CONTROLLER_SUPER_SLOW_SPEED 0x000c0000
//#define DAQ_FIFO_ENABLE 0x00100000 commented out as it // #define DAQ_FIFO_ENABLE 0x00100000 commented out as it
// is not used anywhere // is not used anywhere
#define DAQ_REG_CHIP_CMDS_INT_TRIGGER 0x00100000 #define DAQ_REG_CHIP_CMDS_INT_TRIGGER 0x00100000
@ -131,7 +131,8 @@
#define DAQ_NEXPOSURERS_ACTIVATE_AUTO_SUBIMAGING 0x20000000 #define DAQ_NEXPOSURERS_ACTIVATE_AUTO_SUBIMAGING 0x20000000
#define DAQ_NEXPOSURERS_ACTIVATE_RATE_CORRECTION 0x40000000 #define DAQ_NEXPOSURERS_ACTIVATE_RATE_CORRECTION 0x40000000
//#define DAQ_MASTER_HALF_MODULE 0x80000000 currently not // #define DAQ_MASTER_HALF_MODULE 0x80000000 currently
// not
// used // used
// chips static bits // chips static bits

2
slsDetectorServers/eigerDetectorServer/xfs_types.h
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@ -2,7 +2,7 @@
// Copyright (C) 2021 Contributors to the SLS Detector Package // Copyright (C) 2021 Contributors to the SLS Detector Package
#pragma once #pragma once
//#include "types.h" // #include "types.h"
#include <stdint.h> #include <stdint.h>
/******************************************************************************/ /******************************************************************************/
/* types */ /* types */

2
slsDetectorServers/eigerDetectorServer/xparameters.h
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@ -92,7 +92,7 @@ XPAR_PLB_LL_FIFO_AURORA_DUAL_CTRL_FEB_LEFT_BASEADDR
#define XPAR_PLB_LL_FIFO_AURORA_DUAL_CTRL_FEB_LEFT_HIGHADDR 0xC410FFFF #define XPAR_PLB_LL_FIFO_AURORA_DUAL_CTRL_FEB_LEFT_HIGHADDR 0xC410FFFF
/* Definitions for a new memory */ /* Definitions for a new memory */
//#define XPAR_PLB_LL_NEW_MEMORY 0xD1000000//0xD1000084//0xC4200000 // #define XPAR_PLB_LL_NEW_MEMORY 0xD1000000//0xD1000084//0xC4200000
/* Definitions for peripheral PLB_LL_FIFO_AURORA_DUAL_CTRL_FEB_RIGHT */ /* Definitions for peripheral PLB_LL_FIFO_AURORA_DUAL_CTRL_FEB_RIGHT */
#define XPAR_PLB_LL_FIFO_AURORA_DUAL_CTRL_FEB_RIGHT_BASEADDR 0xC4110000 #define XPAR_PLB_LL_FIFO_AURORA_DUAL_CTRL_FEB_RIGHT_BASEADDR 0xC4110000

40
slsDetectorServers/gotthardDetectorServer/RegisterDefs.h
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@ -22,13 +22,13 @@
((0x1 << GAIN_CONFGAIN_OFST) & GAIN_CONFGAIN_MSK) ((0x1 << GAIN_CONFGAIN_OFST) & GAIN_CONFGAIN_MSK)
/** Flow Control register */ /** Flow Control register */
//#define FLOW_CONTROL_REG (0x11 << MEM_MAP_SHIFT) // #define FLOW_CONTROL_REG (0x11 << MEM_MAP_SHIFT)
/** Flow Status register */ /** Flow Status register */
//#define FLOW_STATUS_REG (0x12 << MEM_MAP_SHIFT) // #define FLOW_STATUS_REG (0x12 << MEM_MAP_SHIFT)
/** Frame register */ /** Frame register */
//#define FRAME_REG (0x13 << MEM_MAP_SHIFT) // #define FRAME_REG (0x13 << MEM_MAP_SHIFT)
/** Multi Purpose register */ /** Multi Purpose register */
#define MULTI_PURPOSE_REG (0x14 << MEM_MAP_SHIFT) #define MULTI_PURPOSE_REG (0x14 << MEM_MAP_SHIFT)
@ -79,7 +79,7 @@
((0x0007f << DAQ_PCKT_LNGTH_OFST) & DAQ_PCKT_LNGTH_MSK) ((0x0007f << DAQ_PCKT_LNGTH_OFST) & DAQ_PCKT_LNGTH_MSK)
/** Time From Start register */ /** Time From Start register */
//#define TIME_FROM_START_REG (0x16 << MEM_MAP_SHIFT) // #define TIME_FROM_START_REG (0x16 << MEM_MAP_SHIFT)
/** DAC Control register */ /** DAC Control register */
#define SPI_REG (0x17 << MEM_MAP_SHIFT) #define SPI_REG (0x17 << MEM_MAP_SHIFT)
@ -139,7 +139,7 @@
((0x1b << ADC_SYNC_ENET_DELAY_OFST) & ADC_SYNC_ENET_DELAY_MSK) ((0x1b << ADC_SYNC_ENET_DELAY_OFST) & ADC_SYNC_ENET_DELAY_MSK)
/** Time From Start register */ /** Time From Start register */
//#define MU_TIME_REG (0x1a << MEM_MAP_SHIFT) // #define MU_TIME_REG (0x1a << MEM_MAP_SHIFT)
/** Temperatre SPI In register */ /** Temperatre SPI In register */
#define TEMP_SPI_IN_REG (0x1b << MEM_MAP_SHIFT) #define TEMP_SPI_IN_REG (0x1b << MEM_MAP_SHIFT)
@ -171,7 +171,7 @@
#define ENET_CONF_REG (0x1e << MEM_MAP_SHIFT) #define ENET_CONF_REG (0x1e << MEM_MAP_SHIFT)
/** Write TSE Shadow register */ /** Write TSE Shadow register */
//#define WRITE_TSE_SHADOW_REG (0x1f << MEM_MAP_SHIFT) // #define WRITE_TSE_SHADOW_REG (0x1f << MEM_MAP_SHIFT)
/** High Voltage register */ /** High Voltage register */
#define HV_REG (0x20 << MEM_MAP_SHIFT) #define HV_REG (0x20 << MEM_MAP_SHIFT)
@ -288,10 +288,10 @@
((0x4 << EXT_SIGNAL_OFST) & EXT_SIGNAL_MSK) ((0x4 << EXT_SIGNAL_OFST) & EXT_SIGNAL_MSK)
/** Look at me register */ /** Look at me register */
//#define LOOK_AT_ME_REG (0x28 << MEM_MAP_SHIFT) // #define LOOK_AT_ME_REG (0x28 << MEM_MAP_SHIFT)
/** FPGA SVN register */ /** FPGA SVN register */
//#define FPGA_SVN_REG (0x29 << MEM_MAP_SHIFT) // #define FPGA_SVN_REG (0x29 << MEM_MAP_SHIFT)
/** Chip of Interest register */ /** Chip of Interest register */
#define CHIP_OF_INTRST_REG (0x2a << MEM_MAP_SHIFT) #define CHIP_OF_INTRST_REG (0x2a << MEM_MAP_SHIFT)
@ -303,7 +303,7 @@
(0x0000FFFF << CHIP_OF_INTRST_NUM_CHNNLS_OFST) (0x0000FFFF << CHIP_OF_INTRST_NUM_CHNNLS_OFST)
/** Out MUX register */ /** Out MUX register */
//#define OUT_MUX_REG (0x2b << MEM_MAP_SHIFT) // #define OUT_MUX_REG (0x2b << MEM_MAP_SHIFT)
/** Board Version register */ /** Board Version register */
#define BOARD_REVISION_REG (0x2c << MEM_MAP_SHIFT) #define BOARD_REVISION_REG (0x2c << MEM_MAP_SHIFT)
@ -312,29 +312,29 @@
#define BOARD_REVISION_MSK (0x0000FFFF << BOARD_REVISION_OFST) #define BOARD_REVISION_MSK (0x0000FFFF << BOARD_REVISION_OFST)
#define DETECTOR_TYPE_OFST (16) #define DETECTOR_TYPE_OFST (16)
#define DETECTOR_TYPE_MSK (0x0000000F << DETECTOR_TYPE_OFST) #define DETECTOR_TYPE_MSK (0x0000000F << DETECTOR_TYPE_OFST)
//#define DETECTOR_TYPE_GOTTHARD_VAL (??) // #define DETECTOR_TYPE_GOTTHARD_VAL (??)
#define DETECTOR_TYPE_MOENCH_VAL (2) #define DETECTOR_TYPE_MOENCH_VAL (2)
/** Memory Test register */ /** Memory Test register */
//#define MEMORY_TEST_REG (0x2d << MEM_MAP_SHIFT) // #define MEMORY_TEST_REG (0x2d << MEM_MAP_SHIFT)
/** Hit Threshold register */ /** Hit Threshold register */
//#define HIT_THRESHOLD_REG (0x2e << MEM_MAP_SHIFT) // #define HIT_THRESHOLD_REG (0x2e << MEM_MAP_SHIFT)
/** Hit Count register */ /** Hit Count register */
//#define HIT_COUNT_REG (0x2f << MEM_MAP_SHIFT) // #define HIT_COUNT_REG (0x2f << MEM_MAP_SHIFT)
/* 16 bit Fifo Data register */ /* 16 bit Fifo Data register */
#define FIFO_DATA_REG (0x50 << MEM_MAP_SHIFT) // Not used in FW and SW (16bit) #define FIFO_DATA_REG (0x50 << MEM_MAP_SHIFT) // Not used in FW and SW (16bit)
/** Dacs Set 1 register */ /** Dacs Set 1 register */
//#define DACS_SET_1_REG (0x65 << MEM_MAP_SHIFT) // #define DACS_SET_1_REG (0x65 << MEM_MAP_SHIFT)
/** Dacs Set 2 register */ /** Dacs Set 2 register */
//#define DACS_SET_2_REG (0x66 << MEM_MAP_SHIFT) // #define DACS_SET_2_REG (0x66 << MEM_MAP_SHIFT)
/** Dacs Set 3 register */ /** Dacs Set 3 register */
//#define DACS_SET_3_REG (0x67 << MEM_MAP_SHIFT) // #define DACS_SET_3_REG (0x67 << MEM_MAP_SHIFT)
/* Set Delay 64 bit register */ /* Set Delay 64 bit register */
#define SET_DELAY_LSB_REG (0x68 << MEM_MAP_SHIFT) #define SET_DELAY_LSB_REG (0x68 << MEM_MAP_SHIFT)
@ -377,12 +377,12 @@
#define GET_EXPTIME_MSB_REG (0x7b << MEM_MAP_SHIFT) #define GET_EXPTIME_MSB_REG (0x7b << MEM_MAP_SHIFT)
/* Set Gates 64 bit register */ /* Set Gates 64 bit register */
//#define SET_GATES_LSB_REG (0x7c << MEM_MAP_SHIFT) // #define SET_GATES_LSB_REG (0x7c << MEM_MAP_SHIFT)
//#define SET_GATES_MSB_REG (0x7d << MEM_MAP_SHIFT) // #define SET_GATES_MSB_REG (0x7d << MEM_MAP_SHIFT)
/* Set Gates 64 bit register */ /* Set Gates 64 bit register */
//#define GET_GATES_LSB_REG (0x7e << MEM_MAP_SHIFT) // #define GET_GATES_LSB_REG (0x7e << MEM_MAP_SHIFT)
//#define GET_GATES_MSB_REG (0x7f << MEM_MAP_SHIFT) // #define GET_GATES_MSB_REG (0x7f << MEM_MAP_SHIFT)
/* Dark Image starting address */ /* Dark Image starting address */
#define DARK_IMAGE_REG (0x81 << MEM_MAP_SHIFT) #define DARK_IMAGE_REG (0x81 << MEM_MAP_SHIFT)

2
slsDetectorServers/mythen3DetectorServer/mythen3.c
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@ -39,7 +39,7 @@ patternParameters *setChipStatusRegisterPattern(int csr) {
patword = clearBit(SIGNAL_resCounter, patword); patword = clearBit(SIGNAL_resCounter, patword);
for (int i = 0; i < 8; i++) for (int i = 0; i < 8; i++)
pat->word[iaddr++] = patword; pat->word[iaddr++] = patword;
//#This version of the serializer pushes in the MSB first (compatible with // #This version of the serializer pushes in the MSB first (compatible with
// the CSR bit numbering) // the CSR bit numbering)
for (int ib = nbits - 1; ib >= 0; ib--) { for (int ib = nbits - 1; ib >= 0; ib--) {
if (csr & (1 << ib)) if (csr & (1 << ib))

4
slsDetectorServers/mythen3DetectorServer/mythen3.h
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@ -38,11 +38,11 @@
#define CSR_invpol 4 #define CSR_invpol 4
#define CSR_dpulse 5 #define CSR_dpulse 5
#define CSR_interp 6 #define CSR_interp 6
#define _CSR_C10pre 7 //#default, negative polarity #define _CSR_C10pre 7 // #default, negative polarity
#define CSR_pumprobe 8 #define CSR_pumprobe 8
#define CSR_apulse 9 #define CSR_apulse 9
#define CSR_C15sh 10 #define CSR_C15sh 10
#define CSR_C30sh 11 //#default #define CSR_C30sh 11 // #default
#define CSR_C50sh 12 #define CSR_C50sh 12
#define CSR_C225ACsh \ #define CSR_C225ACsh \
13 // Connects 225fF SHAPER AC cap (1: 225 to shaper, 225 to GND. 0: 450 to 13 // Connects 225fF SHAPER AC cap (1: 225 to shaper, 225 to GND. 0: 450 to

4
slsDetectorServers/slsDetectorServer/src/I2C.c
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@ -106,8 +106,8 @@
(0x0000FFFF << I2C_SDA_HOLD_COUNT_PERIOD_OFST) (0x0000FFFF << I2C_SDA_HOLD_COUNT_PERIOD_OFST)
/** Receive Data Fifo Level register */ /** Receive Data Fifo Level register */
//#define I2C_RX_DATA_FIFO_LVL_OFST (0) // #define I2C_RX_DATA_FIFO_LVL_OFST (0)
//#define I2C_RX_DATA_FIFO_LVL_MSK (0x000000FF << // #define I2C_RX_DATA_FIFO_LVL_MSK (0x000000FF <<
// I2C_RX_DATA_FIFO_LVL_OFST) // I2C_RX_DATA_FIFO_LVL_OFST)
// defines in the fpga // defines in the fpga

2
slsDetectorServers/slsDetectorServer/src/communication_funcs.c
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@ -622,7 +622,7 @@ void getIpAddressinString(char *cip, uint32_t ip) {
inet_ntop(AF_INET, &ip, cip, INET_ADDRSTRLEN); inet_ntop(AF_INET, &ip, cip, INET_ADDRSTRLEN);
#else #else
sprintf(cip, "%d.%d.%d.%d", (ip >> 24) & 0xff, (ip >> 16) & 0xff, sprintf(cip, "%d.%d.%d.%d", (ip >> 24) & 0xff, (ip >> 16) & 0xff,
(ip >> 8) & 0xff, (ip)&0xff); (ip >> 8) & 0xff, (ip) & 0xff);
#endif #endif
} }

12
slsDetectorServers/slsDetectorServer/src/slsDetectorServer_funcs.c
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@ -2014,7 +2014,8 @@ int acquire(int blocking, int file_des) {
// chipv1.1 has to be configured before acquisition // chipv1.1 has to be configured before acquisition
if (getChipVersion() == 11 && !isChipConfigured()) { if (getChipVersion() == 11 && !isChipConfigured()) {
ret = FAIL; ret = FAIL;
strcpy(mess, "Could not start acquisition. Chip is not configured. " strcpy(mess,
"Could not start acquisition. Chip is not configured. "
"Power it on to configure it.\n"); "Power it on to configure it.\n");
LOG(logERROR, (mess)); LOG(logERROR, (mess));
} else } else
@ -2034,7 +2035,8 @@ int acquire(int blocking, int file_des) {
getReadoutMode() == DIGITAL_AND_TRANSCEIVER) && getReadoutMode() == DIGITAL_AND_TRANSCEIVER) &&
(getNumDigitalSamples() <= 0)) { (getNumDigitalSamples() <= 0)) {
ret = FAIL; ret = FAIL;
sprintf(mess, sprintf(
mess,
"Could not start acquisition. Invalid number of digital " "Could not start acquisition. Invalid number of digital "
"samples: %d.\n", "samples: %d.\n",
getNumDigitalSamples()); getNumDigitalSamples());
@ -2070,7 +2072,8 @@ int acquire(int blocking, int file_des) {
uint32_t sourceip = getDetectorIP(); uint32_t sourceip = getDetectorIP();
char src_ip[INET_ADDRSTRLEN]; char src_ip[INET_ADDRSTRLEN];
getIpAddressinString(src_ip, sourceip); getIpAddressinString(src_ip, sourceip);
sprintf(mess, sprintf(
mess,
"Invalid udp source ip address for this detector. Must " "Invalid udp source ip address for this detector. Must "
"be " "be "
"same as hardware detector ip address %s in 1G readout " "same as hardware detector ip address %s in 1G readout "
@ -2086,7 +2089,8 @@ int acquire(int blocking, int file_des) {
LOG(logERROR, (mess)); LOG(logERROR, (mess));
} else if (sharedMemory_getScanStatus() == RUNNING) { } else if (sharedMemory_getScanStatus() == RUNNING) {
ret = FAIL; ret = FAIL;
strcpy(mess, "Could not start acquisition because a scan is " strcpy(mess,
"Could not start acquisition because a scan is "
"already running!\n"); "already running!\n");
LOG(logERROR, (mess)); LOG(logERROR, (mess));
} else { } else {

4
slsDetectorSoftware/src/DetectorImpl.h
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@ -79,7 +79,9 @@ class DetectorImpl : public virtual slsDetectorDefs {
explicit DetectorImpl(int detector_index = 0, bool verify = true, explicit DetectorImpl(int detector_index = 0, bool verify = true,
bool update = true); bool update = true);
template <class CT> struct NonDeduced { using type = CT; }; template <class CT> struct NonDeduced {
using type = CT;
};
template <typename RT, typename... CT> template <typename RT, typename... CT>
Result<RT> Parallel(RT (Module::*somefunc)(CT...), Result<RT> Parallel(RT (Module::*somefunc)(CT...),
std::vector<int> positions, std::vector<int> positions,

2
slsSupportLib/include/sls/md5.h
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@ -130,7 +130,7 @@ extern "C" {
ll = (c)->D; \ ll = (c)->D; \
(void)HOST_l2c(ll, (s)); \ (void)HOST_l2c(ll, (s)); \
} while (0) } while (0)
#define ROTATE(a, n) (((a) << (n)) | (((a)&0xffffffff) >> (32 - (n)))) #define ROTATE(a, n) (((a) << (n)) | (((a) & 0xffffffff) >> (32 - (n))))
#if defined(DATA_ORDER_IS_BIG_ENDIAN) #if defined(DATA_ORDER_IS_BIG_ENDIAN)
#define HOST_c2l(c, l) \ #define HOST_c2l(c, l) \