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New server for JF to go with the new FW (#232)

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* Modified Jungfrau speed settings for HW1.0 - FW fix version 1.1.1, compilation date 210218

* Corrected bug. DBIT clk phase is implemented in both HW version 1.0 and 2.0. Previous version did not update the DBIT phase shift on the configuration of a speed.

The new server has been compiled

Co-authored-by: lopez_c <carlos.lopez-cuenca@psi.ch>
This commit is contained in:
Erik Fröjdh 2021-02-25 10:26:39 +01:00 committed by GitHub
parent 10b315c2bd
commit e8fe203940
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GPG Key ID: 4AEE18F83AFDEB23
3 changed files with 7 additions and 10 deletions
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BIN
slsDetectorServers/jungfrauDetectorServer/bin/jungfrauDetectorServer_developer
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7
slsDetectorServers/jungfrauDetectorServer/slsDetectorFunctionList.c
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@ -1396,11 +1396,8 @@ int setClockDivider(enum CLKINDEX ind, int val) {
setPhase(ADC_CLK, adcPhase, 0);
LOG(logINFO, ("\tSet ADC Phase Reg to %d\n", adcPhase));
// only implemented in the new boards now
if (!isHardwareVersion2()) {
setPhase(DBIT_CLK, dbitPhase, 0);
LOG(logINFO, ("\tSet DBIT Phase Reg to %d\n", dbitPhase));
}
setPhase(DBIT_CLK, dbitPhase, 0);
LOG(logINFO, ("\tSet DBIT Phase Reg to %d\n", dbitPhase));
return OK;
}

10
slsDetectorServers/jungfrauDetectorServer/slsDetectorServer_defs.h
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@ -3,7 +3,7 @@
#include "sls/sls_detector_defs.h"
#define MIN_REQRD_VRSN_T_RD_API 0x171220
#define REQRD_FRMWRE_VRSN_BOARD2 0x200724 // 1.0 pcb
#define REQRD_FRMWRE_VRSN_BOARD2 0x210218 // 1.0 pcb
#define REQRD_FRMWRE_VRSN 0x200721 // 2.0 pcb
#define CTRL_SRVR_INIT_TIME_US (300 * 1000)
@ -113,8 +113,8 @@ enum CLKINDEX { RUN_CLK, ADC_CLK, DBIT_CLK, NUM_CLOCKS };
#define ADC_OFST_FULL_SPEED_VAL (0x10) // 2.0 pcb
#define ADC_OFST_HALF_SPEED_VAL (0x08) // 2.0 pcb
#define ADC_OFST_QUARTER_SPEED_VAL (0x04) // 2.0 pcb
#define ADC_OFST_HALF_SPEED_BOARD2_VAL (0x13) // 1.0 pcb (2 resistor network)
#define ADC_OFST_QUARTER_SPEED_BOARD2_VAL (0x0b) // 1.0 pcb (2 resistor network)
#define ADC_OFST_HALF_SPEED_BOARD2_VAL (0x10) // 1.0 pcb (2 resistor network)
#define ADC_OFST_QUARTER_SPEED_BOARD2_VAL (0x08) // 1.0 pcb (2 resistor network)
#define ADC_PORT_INVERT_VAL (0x5A5A5A5A)
#define ADC_PORT_INVERT_BOARD2_VAL (0x453b2a9c)
@ -140,8 +140,8 @@ enum CLKINDEX { RUN_CLK, ADC_CLK, DBIT_CLK, NUM_CLOCKS };
#define ADC_PHASE_FULL_SPEED (150) // 2.0 pcb
#define ADC_PHASE_HALF_SPEED (200) // 2.0 pcb
#define ADC_PHASE_QUARTER_SPEED (200) // 2.0 pcb
#define ADC_PHASE_HALF_SPEED_BOARD2 (75) // 1.0 pcb (2 resistor network)
#define ADC_PHASE_QUARTER_SPEED_BOARD2 (75) // 1.0 pcb (2 resistor network)
#define ADC_PHASE_HALF_SPEED_BOARD2 (110) // 1.0 pcb (2 resistor network)
#define ADC_PHASE_QUARTER_SPEED_BOARD2 (220) // 1.0 pcb (2 resistor network)
#define DBIT_PHASE_FULL_SPEED (85) // 2.0 pcb
#define DBIT_PHASE_HALF_SPEED (150) // 2.0 pcb