mirror of
https://github.com/slsdetectorgroup/slsDetectorPackage.git
synced 2025-06-12 21:07:13 +02:00
gotthard2: updated register map; powerchip checking detector type; internal and external period, frames, exptime; set/get delay, get actualtime, measurement, framesfromstart enabled; which detector comment updated in cmdproxy, detector and slsdetector
This commit is contained in:
@ -14,13 +14,33 @@
|
||||
|
||||
/* Base addresses 0x1806 0000 ---------------------------------------------*/
|
||||
/* General purpose control and status registers */
|
||||
#define BASE_CONTROL (0x0000)
|
||||
/* Acquisition? TODO */
|
||||
#define BASE_ACQUISITION (0x0200)
|
||||
#define BASE_CONTROL (0x0000) // 0x1806_0000 - 0x1806_00FF
|
||||
// https://git.psi.ch/sls_detectors_firmware/gotthard_II_mcb/blob/master/code/hdl/ctrl/ctrl.vhd
|
||||
|
||||
/* ASIC Control */
|
||||
#define BASE_ASIC (0x0100) // 0x1806_0100 - 0x1806_011F
|
||||
// https://git.psi.ch/sls_detectors_firmware/gotthard_II_mcb/blob/master/code/hdl/asic/asic_ctrl.vhd
|
||||
|
||||
/* ASIC Digital Interface. Data recovery core */
|
||||
#define BASE_ADIF (0x0120) // 0x1806_0120 - 0x1806_012F
|
||||
// https://git.psi.ch/sls_detectors_firmware/gotthard_II_mcb/blob/master/code/hdl/adif/adif_ctrl.vhd
|
||||
|
||||
/* Formatting of data core */
|
||||
#define BASE_FMT (0x0130) // 0x1806_0130 - 0x1806_013F
|
||||
|
||||
/* Packetizer */
|
||||
#define BASE_PKT (0x0140) // 0x1806_0140 - 0x1806_014F
|
||||
// https://git.psi.ch/sls_detectors_firmware/gotthard_II_mcb/blob/master/code/hdl/pkt/pkt_ctrl.vhd
|
||||
|
||||
/* Flow control and status registers */
|
||||
#define BASE_FLOW_CONTROL (0x00200) // 0x1806_0200 - 0x1806_02FF
|
||||
// https://git.psi.ch/sls_detectors_firmware/vhdl_library/blob/f37608230b4721661f29aacc20124555705ee705/flow/flow_ctrl.vhd
|
||||
|
||||
/* UDP datagram generator */
|
||||
#define BASE_UDP_RAM (0x01000) // 0x1806_1000 - 0x1806_1FFF
|
||||
|
||||
|
||||
|
||||
/* Clock Generation registers ------------------------------------------------------*/
|
||||
#define PLL_RESET_REG (0x00 * REG_OFFSET + BASE_CLK_GENERATION)
|
||||
|
||||
@ -30,6 +50,7 @@
|
||||
#define PLL_RESET_SYSTEM_MSK (0x00000001 << PLL_RESET_SYSTEM_OFST)
|
||||
|
||||
|
||||
|
||||
/* Control registers --------------------------------------------------*/
|
||||
|
||||
/* Module Control Board Serial Number register */
|
||||
@ -61,11 +82,6 @@
|
||||
/* Status register */
|
||||
#define STATUS_REG (0x04 * REG_OFFSET + BASE_CONTROL)
|
||||
|
||||
#ifdef VIRTUAL
|
||||
#define RUN_BUSY_OFST (0)
|
||||
#define RUN_BUSY_MSK (0x00000001 << RUN_BUSY_OFST)
|
||||
#endif
|
||||
|
||||
/* Look at me read only register */
|
||||
#define LOOK_AT_ME_REG (0x05 * REG_OFFSET + BASE_CONTROL)
|
||||
|
||||
@ -88,43 +104,113 @@
|
||||
#define CONTROL_PRPHRL_RST_MSK (0x00000001 << CONTROL_PRPHRL_RST_OFST)
|
||||
#define CONTROL_CLR_ACQSTN_FIFO_OFST (15)
|
||||
#define CONTROL_CLR_ACQSTN_FIFO_MSK (0x00000001 << CONTROL_CLR_ACQSTN_FIFO_OFST)
|
||||
|
||||
/* Pattern IO Control 64 bit register */
|
||||
#define PATTERN_IO_CTRL_LSB_REG (0x22 * REG_OFFSET + BASE_CONTROL)
|
||||
#define PATTERN_IO_CTRL_MSB_REG (0x23 * REG_OFFSET + BASE_CONTROL)
|
||||
#define CONTROL_PWR_CHIP_OFST (31)
|
||||
#define CONTROL_PWR_CHIP_MSK (0x00000001 << CONTROL_PWR_CHIP_OFST)
|
||||
|
||||
/** DTA Offset Register */
|
||||
#define DTA_OFFSET_REG (0x24 * REG_OFFSET + BASE_CONTROL)
|
||||
|
||||
|
||||
|
||||
/* ASIC registers --------------------------------------------------*/
|
||||
|
||||
/* ASIC Config register */
|
||||
#define ASIC_CONFIG_REG (0x00 * REG_OFFSET + BASE_ASIC)
|
||||
|
||||
#define ASIC_CONFIG_RUN_MODE_OFST (0)
|
||||
#define ASIC_CONFIG_RUN_MODE_MSK (0x00000003 << ASIC_CONFIG_RUN_MODE_OFST)
|
||||
#define ASIC_CONFIG_RUN_MODE_INT_BURST_VAL ((0x1 << ASIC_CONFIG_RUN_MODE_OFST) & ASIC_CONFIG_RUN_MODE_MSK)
|
||||
#define ASIC_CONFIG_RUN_MODE_CONT_VAL ((0x2 << ASIC_CONFIG_RUN_MODE_OFST) & ASIC_CONFIG_RUN_MODE_MSK)
|
||||
#define ASIC_CONFIG_RUN_MODE_EXT_BURST_VAL ((0x3 << ASIC_CONFIG_RUN_MODE_OFST) & ASIC_CONFIG_RUN_MODE_MSK)
|
||||
#define ASIC_CONFIG_GAIN_OFST (4)
|
||||
#define ASIC_CONFIG_GAIN_MSK (0x00000003 << ASIC_CONFIG_GAIN_OFST)
|
||||
#define ASIC_CONFIG_RST_DAC_OFST (15)
|
||||
#define ASIC_CONFIG_RST_DAC_MSK (0x00000001 << ASIC_CONFIG_RST_DAC_OFST)
|
||||
#define ASIC_CONFIG_DONE_OFST (31)
|
||||
#define ASIC_CONFIG_DONE_MSK (0x00000001 << ASIC_CONFIG_DONE_OFST)
|
||||
|
||||
/* ASIC Internal Frames Register */
|
||||
#define ASIC_INT_FRAMES_REG (0x01 * REG_OFFSET + BASE_ASIC)
|
||||
|
||||
#define ASIC_INT_FRAMES_OFST (0)
|
||||
#define ASIC_INT_FRAMES_MSK (0x00000FFF << ASIC_INT_FRAMES_OFST)
|
||||
|
||||
/* ASIC Period 64bit Register */
|
||||
#define ASIC_INT_PERIOD_LSB_REG (0x02 * REG_OFFSET + BASE_ASIC)
|
||||
#define ASIC_INT_PERIOD_MSB_REG (0x03 * REG_OFFSET + BASE_ASIC)
|
||||
|
||||
/* ASIC Exptime 64bit Register */
|
||||
#define ASIC_INT_EXPTIME_LSB_REG (0x04 * REG_OFFSET + BASE_ASIC)
|
||||
#define ASIC_INT_EXPTIME_MSB_REG (0x05 * REG_OFFSET + BASE_ASIC)
|
||||
|
||||
|
||||
/* Flow control registers --------------------------------------------------*/
|
||||
|
||||
/* Flow status Register*/
|
||||
#define FLOW_STATUS_REG (0x00 * REG_OFFSET + BASE_FLOW_CONTROL)
|
||||
#define FLOW_STATUS_RUN_BUSY_OFST (0)
|
||||
#define FLOW_STATUS_RUN_BUSY_MSK (0x00000001 << FLOW_STATUS_RUN_BUSY_OFST)
|
||||
#define FLOW_STATUS_WAIT_FOR_TRGGR_OFST (3)
|
||||
#define FLOW_STATUS_WAIT_FOR_TRGGR_MSK (0x00000001 << FLOW_STATUS_WAIT_FOR_TRGGR_OFST)
|
||||
#define FLOW_STATUS_DLY_BFRE_TRGGR_OFST (4)
|
||||
#define FLOW_STATUS_DLY_BFRE_TRGGR_MSK (0x00000001 << FLOW_STATUS_DLY_BFRE_TRGGR_OFST)
|
||||
#define FLOW_STATUS_FIFO_FULL_OFST (5)
|
||||
#define FLOW_STATUS_FIFO_FULL_MSK (0x00000001 << FLOW_STATUS_FIFO_FULL_OFST)
|
||||
#define FLOW_STATUS_DLY_AFTR_TRGGR_OFST (15)
|
||||
#define FLOW_STATUS_DLY_AFTR_TRGGR_MSK (0x00000001 << FLOW_STATUS_DLY_AFTR_TRGGR_OFST)
|
||||
#define FLOW_STATUS_CSM_BUSY_OFST (17)
|
||||
#define FLOW_STATUS_CSM_BUSY_MSK (0x00000001 << FLOW_STATUS_CSM_BUSY_OFST)
|
||||
|
||||
/* Delay left 64bit Register */
|
||||
#define GET_DELAY_LSB_REG (0x02 * REG_OFFSET + BASE_FLOW_CONTROL)
|
||||
#define GET_DELAY_MSB_REG (0x03 * REG_OFFSET + BASE_FLOW_CONTROL)
|
||||
|
||||
/* Acquisition registers --------------------------------------------------*/
|
||||
//TODO
|
||||
/* Triggers left 64bit Register */
|
||||
#define GET_CYCLES_LSB_REG (0x10 + BASE_ACQUISITION)
|
||||
#define GET_CYCLES_MSB_REG (0x14 + BASE_ACQUISITION)
|
||||
#define GET_CYCLES_LSB_REG (0x04 * REG_OFFSET + BASE_FLOW_CONTROL)
|
||||
#define GET_CYCLES_MSB_REG (0x05 * REG_OFFSET + BASE_FLOW_CONTROL)
|
||||
|
||||
/* Frames left 64bit Register */
|
||||
#define GET_FRAMES_LSB_REG (0x18 + BASE_ACQUISITION)
|
||||
#define GET_FRAMES_MSB_REG (0x1C + BASE_ACQUISITION)
|
||||
#define GET_FRAMES_LSB_REG (0x06 * REG_OFFSET + BASE_FLOW_CONTROL)
|
||||
#define GET_FRAMES_MSB_REG (0x07 * REG_OFFSET + BASE_FLOW_CONTROL)
|
||||
|
||||
/* Period left 64bit Register */
|
||||
#define GET_PERIOD_LSB_REG (0x08 * REG_OFFSET + BASE_FLOW_CONTROL)
|
||||
#define GET_PERIOD_MSB_REG (0x09 * REG_OFFSET + BASE_FLOW_CONTROL)
|
||||
|
||||
/* Time from Start 64 bit register */
|
||||
#define TIME_FROM_START_LSB_REG (0x0A * REG_OFFSET + BASE_FLOW_CONTROL)
|
||||
#define TIME_FROM_START_MSB_REG (0x0B * REG_OFFSET + BASE_FLOW_CONTROL)
|
||||
|
||||
/* Get Frames from Start 64 bit register (frames from last reset using CONTROL_CRST) */
|
||||
#define FRAMES_FROM_START_LSB_REG (0x0C * REG_OFFSET + BASE_FLOW_CONTROL)
|
||||
#define FRAMES_FROM_START_MSB_REG (0x0D * REG_OFFSET + BASE_FLOW_CONTROL)
|
||||
|
||||
/* Measurement Time 64 bit register (timestamp at a frame start until reset)*/
|
||||
#define START_FRAME_TIME_LSB_REG (0x0E * REG_OFFSET + BASE_FLOW_CONTROL)
|
||||
#define START_FRAME_TIME_MSB_REG (0x0F * REG_OFFSET + BASE_FLOW_CONTROL)
|
||||
|
||||
/* Delay 64bit Write-register */
|
||||
#define SET_DELAY_LSB_REG (0x88 + BASE_ACQUISITION)
|
||||
#define SET_DELAY_MSB_REG (0x8C + BASE_ACQUISITION)
|
||||
#define SET_DELAY_LSB_REG (0x22 * REG_OFFSET + BASE_FLOW_CONTROL)
|
||||
#define SET_DELAY_MSB_REG (0x23 * REG_OFFSET + BASE_FLOW_CONTROL)
|
||||
|
||||
/* Cylces 64bit Write-register */
|
||||
#define SET_CYCLES_LSB_REG (0x90 + BASE_ACQUISITION)
|
||||
#define SET_CYCLES_MSB_REG (0x94 + BASE_ACQUISITION)
|
||||
#define SET_CYCLES_LSB_REG (0x24 * REG_OFFSET + BASE_FLOW_CONTROL)
|
||||
#define SET_CYCLES_MSB_REG (0x25 * REG_OFFSET + BASE_FLOW_CONTROL)
|
||||
|
||||
/* Frames 64bit Write-register */
|
||||
#define SET_FRAMES_LSB_REG (0x98 + BASE_ACQUISITION)
|
||||
#define SET_FRAMES_MSB_REG (0x9C + BASE_ACQUISITION)
|
||||
#define SET_FRAMES_LSB_REG (0x26 * REG_OFFSET + BASE_FLOW_CONTROL)
|
||||
#define SET_FRAMES_MSB_REG (0x27 * REG_OFFSET + BASE_FLOW_CONTROL)
|
||||
|
||||
/* Period 64bit Write-register */
|
||||
#define SET_PERIOD_LSB_REG (0xA0 + BASE_ACQUISITION)
|
||||
#define SET_PERIOD_MSB_REG (0xA4 + BASE_ACQUISITION)
|
||||
#define SET_PERIOD_LSB_REG (0x28 * REG_OFFSET + BASE_FLOW_CONTROL)
|
||||
#define SET_PERIOD_MSB_REG (0x29 * REG_OFFSET + BASE_FLOW_CONTROL)
|
||||
|
||||
/* Exptime 64bit Write-register */
|
||||
#define SET_EXPTIME_LSB_REG (0xA8 + BASE_ACQUISITION)
|
||||
#define SET_EXPTIME_MSB_REG (0xBC + BASE_ACQUISITION)
|
||||
/* External Signal register */
|
||||
#define EXT_SIGNAL_REG (0x30 * REG_OFFSET + BASE_FLOW_CONTROL)
|
||||
|
||||
#define EXT_SIGNAL_OFST (0)
|
||||
#define EXT_SIGNAL_MSK (0x00000001 << EXT_SIGNAL_OFST)
|
||||
|
||||
/* Trigger Delay 64 bit register */
|
||||
#define SET_TRIGGER_DELAY_LSB_REG (0x32 * REG_OFFSET + BASE_FLOW_CONTROL)
|
||||
#define SET_TRIGGER_DELAY_MSB_REG (0x33 * REG_OFFSET + BASE_FLOW_CONTROL)
|
||||
|
||||
Binary file not shown.
@ -39,13 +39,14 @@ uint32_t clkFrequency[NUM_CLOCKS] = {0, 0, 0, 0, 0, 0};
|
||||
int highvoltage = 0;
|
||||
int dacValues[NDAC] = {0};
|
||||
int onChipdacValues[ONCHIP_NDAC][NCHIP] = {0};
|
||||
int defaultDacValues[NDAC] = {0};
|
||||
int defaultOnChipdacValues[ONCHIP_NDAC][NCHIP] = {0};
|
||||
int injectedChannelsOffset = 0;
|
||||
int injectedChannelsIncrement = 0;
|
||||
int vetoReference[NCHIP][NCHAN];
|
||||
uint8_t adcConfiguration[NCHIP][NADC];
|
||||
int burstMode = 0;
|
||||
int64_t exptime_ns = 0;
|
||||
int64_t period_ns = 0;
|
||||
int64_t nframes = 0;
|
||||
int detPos[2] = {0, 0};
|
||||
|
||||
int isInitCheckDone() {
|
||||
@ -72,6 +73,7 @@ void basictests() {
|
||||
}
|
||||
return;
|
||||
#else
|
||||
FILE_LOG(logINFOBLUE, ("************ Gotthard2 Server *********************\n"));
|
||||
if (mapCSP0() == FAIL) {
|
||||
strcpy(initErrorMessage,
|
||||
"Could not map to memory. Dangerous to continue.\n");
|
||||
@ -97,7 +99,7 @@ void basictests() {
|
||||
int64_t client_sw_apiversion = getClientServerAPIVersion();
|
||||
uint32_t requiredFirmwareVersion = REQRD_FRMWRE_VRSN;
|
||||
|
||||
FILE_LOG(logINFOBLUE, ("************ Gotthard2 Server *********************\n"
|
||||
FILE_LOG(logINFOBLUE, ("*************************************************\n"
|
||||
"Hardware Version:\t\t 0x%x\n"
|
||||
|
||||
"Detector IP Addr:\t\t 0x%x\n"
|
||||
@ -158,7 +160,6 @@ void basictests() {
|
||||
return;
|
||||
}
|
||||
FILE_LOG(logINFO, ("Compatibility - success\n"));
|
||||
|
||||
#endif
|
||||
}
|
||||
|
||||
@ -352,12 +353,10 @@ void setupDetector() {
|
||||
}
|
||||
for (i = 0; i < NDAC; ++i) {
|
||||
dacValues[i] = 0;
|
||||
defaultDacValues[i] = 0;
|
||||
}
|
||||
for (i = 0; i < ONCHIP_NDAC; ++i) {
|
||||
for (j = 0; j < NCHIP; ++j) {
|
||||
onChipdacValues[i][j] = -1;
|
||||
defaultOnChipdacValues[i][j] = -1;
|
||||
}
|
||||
}
|
||||
for (i = 0; i < NCHIP; ++i) {
|
||||
@ -397,35 +396,10 @@ void setupDetector() {
|
||||
setNumTriggers(DEFAULT_NUM_CYCLES);
|
||||
setExpTime(DEFAULT_EXPTIME);
|
||||
setPeriod(DEFAULT_PERIOD);
|
||||
setDelayAfterTrigger(DEFAULT_DELAY_AFTER_TRIGGER);
|
||||
setTiming(DEFAULT_TIMING_MODE);
|
||||
}
|
||||
|
||||
int setDefaultDacs() {
|
||||
int ret = OK;
|
||||
FILE_LOG(logINFOBLUE, ("Setting Default Dac values\n"));
|
||||
{
|
||||
int idac = 0;
|
||||
for(idac = 0; idac < NDAC; ++idac) {
|
||||
setDAC((enum DACINDEX)idac, defaultDacValues[idac], 0);
|
||||
}
|
||||
}
|
||||
return ret;
|
||||
}
|
||||
|
||||
int setDefaultOnChipDacs() {
|
||||
int ret = OK;
|
||||
FILE_LOG(logINFOBLUE, ("Setting Default On chip Dac values\n"));
|
||||
{
|
||||
int idac = 0, ichip = 0;
|
||||
for(idac = 0; idac < ONCHIP_NDAC; ++idac) {
|
||||
for(ichip = 0; ichip < NCHIP; ++ichip) {
|
||||
setOnChipDAC((enum ONCHIP_DACINDEX)idac, ichip, defaultOnChipdacValues[idac][ichip]);
|
||||
}
|
||||
}
|
||||
}
|
||||
return ret;
|
||||
}
|
||||
|
||||
|
||||
int readConfigFile() {
|
||||
|
||||
if (initError == FAIL) {
|
||||
@ -663,6 +637,31 @@ int readConfigFile() {
|
||||
return initError;
|
||||
}
|
||||
|
||||
/* firmware functions (resets) */
|
||||
|
||||
void cleanFifos() {
|
||||
#ifdef VIRTUAL
|
||||
return;
|
||||
#endif
|
||||
FILE_LOG(logINFO, ("Clearing Acquisition Fifos\n"));
|
||||
bus_w(CONTROL_REG, bus_r(CONTROL_REG) | CONTROL_CLR_ACQSTN_FIFO_MSK);
|
||||
}
|
||||
|
||||
void resetCore() {
|
||||
#ifdef VIRTUAL
|
||||
return;
|
||||
#endif
|
||||
FILE_LOG(logINFO, ("Resetting Core\n"));
|
||||
bus_w(CONTROL_REG, bus_r(CONTROL_REG) | CONTROL_CRE_RST_MSK);
|
||||
}
|
||||
|
||||
void resetPeripheral() {
|
||||
#ifdef VIRTUAL
|
||||
return;
|
||||
#endif
|
||||
FILE_LOG(logINFO, ("Resetting Peripheral\n"));
|
||||
bus_w(CONTROL_REG, bus_r(CONTROL_REG) | CONTROL_PRPHRL_RST_MSK);
|
||||
}
|
||||
|
||||
/* set parameters - dr, roi */
|
||||
|
||||
@ -671,16 +670,16 @@ int setDynamicRange(int dr){
|
||||
}
|
||||
|
||||
|
||||
/* parameters */
|
||||
/* parameters - timer */
|
||||
void setNumFrames(int64_t val) {
|
||||
if (val > 0) {
|
||||
FILE_LOG(logINFO, ("Setting number of frames %lld\n", (long long int)val));
|
||||
set64BitReg(val, SET_FRAMES_LSB_REG, SET_FRAMES_MSB_REG);
|
||||
FILE_LOG(logINFO, ("Setting number of frames %lld [local]\n", (long long int)val));
|
||||
nframes = val;
|
||||
}
|
||||
}
|
||||
|
||||
int64_t getNumFrames() {
|
||||
return get64BitReg(SET_FRAMES_LSB_REG, SET_FRAMES_MSB_REG);
|
||||
return nframes;
|
||||
}
|
||||
|
||||
void setNumTriggers(int64_t val) {
|
||||
@ -699,21 +698,13 @@ int setExpTime(int64_t val) {
|
||||
FILE_LOG(logERROR, ("Invalid exptime: %lld ns\n", (long long int)val));
|
||||
return FAIL;
|
||||
}
|
||||
FILE_LOG(logINFO, ("Setting exptime %lld ns\n", (long long int)val));
|
||||
val *= (1E-9 * READOUT_C0);
|
||||
set64BitReg(val, SET_EXPTIME_LSB_REG, SET_EXPTIME_MSB_REG);
|
||||
|
||||
// validate for tolerance
|
||||
int64_t retval = getExpTime();
|
||||
val /= (1E-9 * READOUT_C0);
|
||||
if (val != retval) {
|
||||
return FAIL;
|
||||
}
|
||||
FILE_LOG(logINFO, ("Setting exptime %lld ns [local]\n", (long long int)val));
|
||||
exptime_ns = val;
|
||||
return OK;
|
||||
}
|
||||
|
||||
int64_t getExpTime() {
|
||||
return get64BitReg(SET_EXPTIME_LSB_REG, SET_EXPTIME_MSB_REG) / (1E-9 * READOUT_C0);
|
||||
return exptime_ns;
|
||||
}
|
||||
|
||||
int setPeriod(int64_t val) {
|
||||
@ -721,9 +712,65 @@ int setPeriod(int64_t val) {
|
||||
FILE_LOG(logERROR, ("Invalid period: %lld ns\n", (long long int)val));
|
||||
return FAIL;
|
||||
}
|
||||
FILE_LOG(logINFO, ("Setting period %lld ns\n", (long long int)val));
|
||||
FILE_LOG(logINFO, ("Setting period %lld ns [local]\n", (long long int)val));
|
||||
period_ns = val;
|
||||
return OK;
|
||||
}
|
||||
|
||||
int64_t getPeriod() {
|
||||
return period_ns;
|
||||
}
|
||||
|
||||
void setNumFramesBurst(int64_t val) {
|
||||
FILE_LOG(logINFO, ("Setting number of frames %d [Burst mode]\n", (int)val));
|
||||
bus_w(ASIC_INT_FRAMES_REG, bus_r(ASIC_INT_FRAMES_REG) | (((int)val << ASIC_INT_FRAMES_OFST) & ASIC_INT_FRAMES_MSK));
|
||||
}
|
||||
|
||||
int64_t getNumFramesBurst() {
|
||||
return ((bus_r(ASIC_INT_FRAMES_REG) & ASIC_INT_FRAMES_MSK) >> ASIC_INT_FRAMES_OFST);
|
||||
}
|
||||
|
||||
void setNumFramesCont(int64_t val) {
|
||||
FILE_LOG(logINFO, ("Setting number of frames %lld [Continuous mode]\n", (long long int)val));
|
||||
set64BitReg(val, SET_FRAMES_LSB_REG, SET_FRAMES_MSB_REG);
|
||||
}
|
||||
|
||||
int64_t getNumFramesCont() {
|
||||
return get64BitReg(SET_FRAMES_LSB_REG, SET_FRAMES_MSB_REG);
|
||||
}
|
||||
|
||||
int setExptimeBurst(int64_t val) {
|
||||
FILE_LOG(logINFO, ("Setting exptime %lld ns [Burst mode]\n", (long long int)val));
|
||||
return setExptimeBoth(val);
|
||||
}
|
||||
|
||||
int setExptimeCont(int64_t val) {
|
||||
FILE_LOG(logINFO, ("Setting exptime %lld ns [Continuous mode]\n", (long long int)val));
|
||||
return setExptimeBoth(val);
|
||||
}
|
||||
|
||||
int setExptimeBoth(int64_t val) {
|
||||
val *= (1E-9 * SYSTEM_C0);
|
||||
set64BitReg(val, SET_PERIOD_LSB_REG, SET_PERIOD_MSB_REG);
|
||||
set64BitReg(val, ASIC_INT_EXPTIME_LSB_REG, ASIC_INT_EXPTIME_MSB_REG);
|
||||
|
||||
// validate for tolerance
|
||||
int64_t retval = getExptimeBoth();
|
||||
val /= (1E-9 * SYSTEM_C0);
|
||||
if (val != retval) {
|
||||
return FAIL;
|
||||
}
|
||||
return OK;
|
||||
}
|
||||
|
||||
int64_t getExptimeBoth() {
|
||||
return get64BitReg(ASIC_INT_EXPTIME_LSB_REG, ASIC_INT_EXPTIME_MSB_REG) / (1E-9 * SYSTEM_C0);
|
||||
}
|
||||
|
||||
|
||||
int setPeriodBurst(int64_t val) {
|
||||
FILE_LOG(logINFO, ("Setting period %lld ns [Burst mode]\n", (long long int)val));
|
||||
val *= (1E-9 * SYSTEM_C0);
|
||||
set64BitReg(val, ASIC_INT_PERIOD_LSB_REG, ASIC_INT_PERIOD_MSB_REG);
|
||||
|
||||
// validate for tolerance
|
||||
int64_t retval = getPeriod();
|
||||
@ -734,8 +781,48 @@ int setPeriod(int64_t val) {
|
||||
return OK;
|
||||
}
|
||||
|
||||
int64_t getPeriod() {
|
||||
return get64BitReg(SET_PERIOD_LSB_REG, SET_PERIOD_MSB_REG)/ (1E-9 * SYSTEM_C0);
|
||||
int64_t getPeriodBurst() {
|
||||
return get64BitReg(ASIC_INT_PERIOD_LSB_REG, ASIC_INT_PERIOD_MSB_REG)/ (1E-9 * SYSTEM_C0);
|
||||
}
|
||||
|
||||
int setPeriodCont(int64_t val) {
|
||||
FILE_LOG(logINFO, ("Setting period %lld ns [Continuous mode]\n", (long long int)val));
|
||||
val *= (1E-9 * FIXED_PLL_FREQUENCY);
|
||||
set64BitReg(val, ASIC_INT_PERIOD_LSB_REG, ASIC_INT_PERIOD_MSB_REG);
|
||||
|
||||
// validate for tolerance
|
||||
int64_t retval = getPeriod();
|
||||
val /= (1E-9 * FIXED_PLL_FREQUENCY);
|
||||
if (val != retval) {
|
||||
return FAIL;
|
||||
}
|
||||
return OK;
|
||||
}
|
||||
|
||||
int64_t getPeriodCont() {
|
||||
return get64BitReg(ASIC_INT_PERIOD_LSB_REG, ASIC_INT_PERIOD_MSB_REG)/ (1E-9 * FIXED_PLL_FREQUENCY);
|
||||
}
|
||||
|
||||
int setDelayAfterTrigger(int64_t val) {
|
||||
if (val < 0) {
|
||||
FILE_LOG(logERROR, ("Invalid delay after trigger: %lld ns\n", (long long int)val));
|
||||
return FAIL;
|
||||
}
|
||||
FILE_LOG(logINFO, ("Setting delay after trigger %lld ns\n", (long long int)val));
|
||||
val *= (1E-9 * FIXED_PLL_FREQUENCY);
|
||||
set64BitReg(val, SET_TRIGGER_DELAY_LSB_REG, SET_TRIGGER_DELAY_MSB_REG);
|
||||
|
||||
// validate for tolerance
|
||||
int64_t retval = getDelayAfterTrigger();
|
||||
val /= (1E-9 * FIXED_PLL_FREQUENCY);
|
||||
if (val != retval) {
|
||||
return FAIL;
|
||||
}
|
||||
return OK;
|
||||
}
|
||||
|
||||
int64_t getDelayAfterTrigger() {
|
||||
return get64BitReg(SET_TRIGGER_DELAY_LSB_REG, SET_TRIGGER_DELAY_MSB_REG) / (1E-9 * FIXED_PLL_FREQUENCY);
|
||||
}
|
||||
|
||||
int64_t getNumFramesLeft() {
|
||||
@ -746,7 +833,25 @@ int64_t getNumTriggersLeft() {
|
||||
return get64BitReg(GET_CYCLES_LSB_REG, GET_CYCLES_MSB_REG);
|
||||
}
|
||||
|
||||
int64_t getDelayAfterTriggerLeft() {
|
||||
return get64BitReg(GET_DELAY_LSB_REG, GET_DELAY_MSB_REG) / (1E-9 * FIXED_PLL_FREQUENCY);
|
||||
}
|
||||
|
||||
int64_t getPeriodLeft() {
|
||||
return get64BitReg(GET_PERIOD_LSB_REG, GET_PERIOD_MSB_REG) / (1E-9 * FIXED_PLL_FREQUENCY);
|
||||
}
|
||||
|
||||
int64_t getFramesFromStart() {
|
||||
return get64BitReg(FRAMES_FROM_START_LSB_REG, FRAMES_FROM_START_MSB_REG);
|
||||
}
|
||||
|
||||
int64_t getActualTime() {
|
||||
return get64BitReg(TIME_FROM_START_LSB_REG, TIME_FROM_START_MSB_REG) / (1E-9 * FIXED_PLL_FREQUENCY * 2);
|
||||
}
|
||||
|
||||
int64_t getMeasurementTime() {
|
||||
return get64BitReg(START_FRAME_TIME_LSB_REG, START_FRAME_TIME_MSB_REG) / (1E-9 * FIXED_PLL_FREQUENCY);
|
||||
}
|
||||
|
||||
/* parameters - dac, hv */
|
||||
int setOnChipDAC(enum ONCHIP_DACINDEX ind, int chipIndex, int val) {
|
||||
@ -866,6 +971,31 @@ int setHighVoltage(int val){
|
||||
return highvoltage;
|
||||
}
|
||||
|
||||
/* parameters - timing */
|
||||
void setTiming( enum timingMode arg){
|
||||
if(arg != GET_TIMING_MODE){
|
||||
switch((int)arg){
|
||||
case AUTO_TIMING:
|
||||
FILE_LOG(logINFO, ("Set Timing: Auto\n"));
|
||||
bus_w(EXT_SIGNAL_REG, bus_r(EXT_SIGNAL_REG) & ~EXT_SIGNAL_MSK);
|
||||
break;
|
||||
case TRIGGER_EXPOSURE:
|
||||
FILE_LOG(logINFO, ("Set Timing: Trigger\n"));
|
||||
bus_w(EXT_SIGNAL_REG, bus_r(EXT_SIGNAL_REG) | EXT_SIGNAL_MSK);
|
||||
break;
|
||||
default:
|
||||
FILE_LOG(logERROR, ("Unknown timing mode %d\n", arg));
|
||||
return;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
enum timingMode getTiming() {
|
||||
if (bus_r(EXT_SIGNAL_REG) == EXT_SIGNAL_MSK)
|
||||
return TRIGGER_EXPOSURE;
|
||||
return AUTO_TIMING;
|
||||
}
|
||||
|
||||
|
||||
int configureMAC() {
|
||||
|
||||
@ -951,9 +1081,9 @@ int configureMAC() {
|
||||
calcChecksum(udp);
|
||||
|
||||
//TODO?
|
||||
//cleanFifos();
|
||||
//resetCore();
|
||||
|
||||
cleanFifos();
|
||||
resetCore();
|
||||
//alignDeserializer();
|
||||
return OK;
|
||||
}
|
||||
|
||||
@ -989,8 +1119,58 @@ void calcChecksum(udp_header* udp) {
|
||||
udp->ip_checksum = checksum;
|
||||
}
|
||||
|
||||
int setDetectorPosition(int pos[]) {
|
||||
memcpy(detPos, pos, sizeof(detPos));
|
||||
return OK;
|
||||
}
|
||||
|
||||
int* getDetectorPosition() {
|
||||
return detPos;
|
||||
}
|
||||
|
||||
// Detector Specific
|
||||
|
||||
int checkDetectorType() {
|
||||
FILE_LOG(logINFO, ("Checking type of module\n"));
|
||||
FILE* fd = fopen(TYPE_FILE_NAME, "r");
|
||||
if (fd == NULL) {
|
||||
FILE_LOG(logERROR, ("Could not open file %s to get type of the module attached\n", TYPE_FILE_NAME));
|
||||
return -1;
|
||||
}
|
||||
char buffer[MAX_STR_LENGTH];
|
||||
memset(buffer, 0, sizeof(buffer));
|
||||
fread (buffer, MAX_STR_LENGTH, sizeof(char), fd);
|
||||
if (strlen(buffer) == 0) {
|
||||
FILE_LOG(logERROR, ("Could not read file %s to get type of the module attached\n", TYPE_FILE_NAME));
|
||||
return -1;
|
||||
}
|
||||
int type = atoi(buffer);
|
||||
if (type > TYPE_TOLERANCE) {
|
||||
FILE_LOG(logERROR, ("No Module attached! Expected %d for Gotthard2, got %d\n", TYPE_GOTTHARD2_MODULE_VAL, type));
|
||||
return -2;
|
||||
}
|
||||
|
||||
if (abs(type - TYPE_GOTTHARD2_MODULE_VAL) > TYPE_TOLERANCE) {
|
||||
FILE_LOG(logERROR, ("Wrong Module attached! Expected %d for Gotthard2, got %d\n", TYPE_GOTTHARD2_MODULE_VAL, type));
|
||||
return FAIL;
|
||||
}
|
||||
return OK;
|
||||
}
|
||||
|
||||
int powerChip (int on){
|
||||
if(on != -1){
|
||||
if(on){
|
||||
FILE_LOG(logINFO, ("Powering chip: on\n"));
|
||||
bus_w(CONTROL_REG, bus_r(CONTROL_REG) | CONTROL_PWR_CHIP_MSK);
|
||||
}
|
||||
else{
|
||||
FILE_LOG(logINFO, ("Powering chip: off\n"));
|
||||
bus_w(CONTROL_REG, bus_r(CONTROL_REG) & ~CONTROL_PWR_CHIP_MSK);
|
||||
}
|
||||
}
|
||||
return ((bus_r(CONTROL_REG) & CONTROL_PWR_CHIP_MSK) >> CONTROL_PWR_CHIP_OFST);
|
||||
}
|
||||
|
||||
int setPhase(enum CLKINDEX ind, int val, int degrees) {
|
||||
if (ind < 0 || ind >= NUM_CLOCKS) {
|
||||
FILE_LOG(logERROR, ("Unknown clock index %d to set phase\n", ind));
|
||||
@ -1471,21 +1651,58 @@ int setBurstMode(int burst) {
|
||||
int getBurstMode() {
|
||||
return burstMode;
|
||||
}
|
||||
|
||||
|
||||
/* aquisition */
|
||||
|
||||
int setDetectorPosition(int pos[]) {
|
||||
memcpy(detPos, pos, sizeof(detPos));
|
||||
int updateAcquisitionRegisters(char* mess) {
|
||||
int64_t exptime_ns = 0;
|
||||
int64_t period_ns = 0;
|
||||
int64_t nframes = 0;
|
||||
|
||||
// burst mode
|
||||
if (burstMode) {
|
||||
// validate #frames in burst mode
|
||||
if (nframes > MAX_FRAMES_IN_BURST_MODE) {
|
||||
sprintf(mess, "Could not start acquisition because number of frames %lld must be <= %d in burst mode.\n", (long long unsigned int)nframes, MAX_FRAMES_IN_BURST_MODE);
|
||||
FILE_LOG(logERROR,(mess));
|
||||
return FAIL;
|
||||
}
|
||||
setNumFramesBurst(nframes);
|
||||
// exptime
|
||||
if (setExptimeBurst(exptime_ns) == FAIL) {
|
||||
sprintf(mess, "Could not start acquisition because exptime could not be set in burst mode. Set %lld ns, got %lld ns.\n", (long long unsigned int)exptime_ns, getExptimeBoth());
|
||||
FILE_LOG(logERROR,(mess));
|
||||
return FAIL;
|
||||
}
|
||||
// period
|
||||
if (setPeriodBurst(period_ns) == FAIL) {
|
||||
sprintf(mess, "Could not start acquisition because period could not be set in burst mode. Set %lld ns, got %lld ns.\n", (long long unsigned int)period_ns, getPeriodBurst());
|
||||
FILE_LOG(logERROR,(mess));
|
||||
return FAIL;
|
||||
}
|
||||
}
|
||||
// continuous
|
||||
else {
|
||||
// frames
|
||||
setNumFramesCont(nframes);
|
||||
// exptime
|
||||
if (setExptimeCont(exptime_ns) == FAIL) {
|
||||
sprintf(mess, "Could not start acquisition because exptime could not be set in continuous mode. Set %lld ns, got %lld ns.\n", (long long unsigned int)exptime_ns, getExptimeBoth());
|
||||
FILE_LOG(logERROR,(mess));
|
||||
return FAIL;
|
||||
}
|
||||
// period
|
||||
if (setPeriodCont(period_ns) == FAIL) {
|
||||
sprintf(mess, "Could not start acquisition because period could not be set in continuous mode. Set %lld ns, got %lld ns.\n", (long long unsigned int)period_ns, getPeriodCont());
|
||||
FILE_LOG(logERROR,(mess));
|
||||
return FAIL;
|
||||
}
|
||||
}
|
||||
return OK;
|
||||
}
|
||||
|
||||
int* getDetectorPosition() {
|
||||
return detPos;
|
||||
}
|
||||
|
||||
int startStateMachine(){
|
||||
if (burstMode && getNumFrames() > MAX_FRAMES_IN_BURST_MODE) {
|
||||
return FAIL;
|
||||
}
|
||||
#ifdef VIRTUAL
|
||||
// create udp socket
|
||||
if(createUDPSocket(0) != OK) {
|
||||
@ -1503,6 +1720,13 @@ int startStateMachine(){
|
||||
FILE_LOG(logINFOGREEN, ("Virtual Acquisition started\n"));
|
||||
return OK;
|
||||
#endif
|
||||
FILE_LOG(logINFOBLUE, ("Starting State Machine\n"));
|
||||
cleanFifos();
|
||||
|
||||
//start state machine
|
||||
bus_w(CONTROL_REG, bus_r(CONTROL_REG) | CONTROL_STRT_ACQSTN_MSK);
|
||||
|
||||
FILE_LOG(logINFO, ("Status Register: %08x\n",bus_r(STATUS_REG)));
|
||||
return OK;
|
||||
}
|
||||
|
||||
@ -1544,6 +1768,7 @@ void* start_timer(void* arg) {
|
||||
// set register frames left
|
||||
}
|
||||
|
||||
closeUDPSocket(0);
|
||||
// set status to idle
|
||||
virtual_status = 0;
|
||||
FILE_LOG(logINFOBLUE, ("Finished Acquiring\n"));
|
||||
@ -1558,6 +1783,9 @@ int stopStateMachine(){
|
||||
virtual_stop = 0;
|
||||
return OK;
|
||||
#endif
|
||||
//stop state machine
|
||||
bus_w(CONTROL_REG, bus_r(CONTROL_REG) | CONTROL_STP_ACQSTN_MSK);
|
||||
FILE_LOG(logINFO, ("Status Register: %08x\n", bus_r(STATUS_REG)));
|
||||
return OK;
|
||||
}
|
||||
|
||||
@ -1571,10 +1799,50 @@ enum runStatus getRunStatus(){
|
||||
return RUNNING;
|
||||
}
|
||||
#endif
|
||||
return IDLE;
|
||||
FILE_LOG(logDEBUG1, ("Getting status\n"));
|
||||
uint32_t retval = bus_r(FLOW_STATUS_REG);
|
||||
FILE_LOG(logINFO, ("Status Register: %08x\n",retval));
|
||||
|
||||
enum runStatus s;
|
||||
|
||||
//running
|
||||
if (retval & FLOW_STATUS_RUN_BUSY_MSK) {
|
||||
if (retval & FLOW_STATUS_WAIT_FOR_TRGGR_MSK) {
|
||||
FILE_LOG(logINFOBLUE, ("Status: WAITING\n"));
|
||||
s = WAITING;
|
||||
} else {
|
||||
if (retval & FLOW_STATUS_DLY_BFRE_TRGGR_MSK) {
|
||||
FILE_LOG(logINFO, ("Status: Delay before Trigger\n"));
|
||||
} else if (retval & FLOW_STATUS_DLY_AFTR_TRGGR_MSK) {
|
||||
FILE_LOG(logINFO, ("Status: Delay after Trigger\n"));
|
||||
}
|
||||
FILE_LOG(logINFOBLUE, ("Status: RUNNING\n"));
|
||||
s = RUNNING;
|
||||
}
|
||||
}
|
||||
|
||||
//not running
|
||||
else {
|
||||
// stopped or error
|
||||
if (retval & FLOW_STATUS_FIFO_FULL_MSK) {
|
||||
FILE_LOG(logINFOBLUE, ("Status: STOPPED\n")); //FIFO FULL??
|
||||
s = STOPPED;
|
||||
} else if (retval & FLOW_STATUS_CSM_BUSY_MSK) {
|
||||
FILE_LOG(logINFOBLUE, ("Status: READ MACHINE BUSY\n"));
|
||||
s = TRANSMITTING;
|
||||
} else if (!retval) {
|
||||
FILE_LOG(logINFOBLUE, ("Status: IDLE\n"));
|
||||
s = IDLE;
|
||||
} else {
|
||||
FILE_LOG(logERROR, ("Status: Unknown status %08x\n", retval));
|
||||
s = ERROR;
|
||||
}
|
||||
}
|
||||
|
||||
return s;
|
||||
}
|
||||
|
||||
void readFrame(int *ret, char *mess){
|
||||
void readFrame(int *ret, char *mess) {
|
||||
// wait for status to be done
|
||||
while(runBusy()){
|
||||
usleep(500);
|
||||
@ -1583,29 +1851,36 @@ void readFrame(int *ret, char *mess){
|
||||
FILE_LOG(logINFOGREEN, ("acquisition successfully finished\n"));
|
||||
return;
|
||||
#endif
|
||||
|
||||
*ret = (int)OK;
|
||||
// frames left to give status
|
||||
int64_t retval = getNumFramesLeft() + 1;
|
||||
|
||||
if ( retval > 0) {
|
||||
FILE_LOG(logERROR, ("No data and run stopped: %lld frames left\n",(long long int)retval));
|
||||
} else {
|
||||
FILE_LOG(logINFOGREEN, ("Acquisition successfully finished\n"));
|
||||
}
|
||||
}
|
||||
|
||||
u_int32_t runBusy() {
|
||||
#ifdef VIRTUAL
|
||||
return virtual_status;
|
||||
#endif
|
||||
#ifdef VIRTUAL
|
||||
u_int32_t s = (bus_r(STATUS_REG) & RUN_BUSY_MSK);
|
||||
u_int32_t s = (bus_r(FLOW_STATUS_REG) & FLOW_STATUS_RUN_BUSY_MSK);
|
||||
FILE_LOG(logDEBUG1, ("Status Register: %08x\n", s));
|
||||
return s;
|
||||
#endif
|
||||
return -1;
|
||||
}
|
||||
|
||||
|
||||
|
||||
/* common */
|
||||
|
||||
int calculateDataBytes(){
|
||||
int calculateDataBytes() {
|
||||
return getTotalNumberOfChannels() * DYNAMIC_RANGE;
|
||||
}
|
||||
|
||||
int getTotalNumberOfChannels(){return ((int)getNumberOfChannelsPerChip() * (int)getNumberOfChips());}
|
||||
int getNumberOfChips(){return NCHIP;}
|
||||
int getNumberOfDACs(){return NDAC;}
|
||||
int getNumberOfChannelsPerChip(){return NCHAN;}
|
||||
int getTotalNumberOfChannels() {return ((int)getNumberOfChannelsPerChip() * (int)getNumberOfChips());}
|
||||
int getNumberOfChips() {return NCHIP;}
|
||||
int getNumberOfDACs() {return NDAC;}
|
||||
int getNumberOfChannelsPerChip() {return NCHAN;}
|
||||
@ -17,22 +17,27 @@
|
||||
#define HV_DRIVER_FILE_NAME ("/etc/devlinks/hvdac")
|
||||
#define DAC_DRIVER_FILE_NAME ("/etc/devlinks/dac")
|
||||
#define ONCHIP_DAC_DRIVER_FILE_NAME ("/etc/devlinks/chipdac")
|
||||
#define TYPE_FILE_NAME ("/etc/devlinks/type")
|
||||
#define CONFIG_FILE ("config.txt")
|
||||
#define DAC_MAX_MV (2048)
|
||||
#define ONCHIP_DAC_MAX_VAL (0x3FF)
|
||||
#define ADU_MAX_VAL (0xFFF)
|
||||
#define ADU_MAX_BITS (12)
|
||||
#define MAX_FRAMES_IN_BURST_MODE (2720)
|
||||
|
||||
#define TYPE_GOTTHARD2_MODULE_VAL (512)
|
||||
#define TYPE_TOLERANCE (10)
|
||||
#define TYPE_NO_MODULE_STARTING_VAL (800)
|
||||
|
||||
/** Default Parameters */
|
||||
#define DEFAULT_NUM_FRAMES (1)
|
||||
#define DEFAULT_NUM_CYCLES (1)
|
||||
#define DEFAULT_EXPTIME (1 * 1000 * 1000) // 1 ms
|
||||
#define DEFAULT_PERIOD (1 * 1000 * 1000 * 1000) // 1 s
|
||||
#define DEFAULT_DELAY_AFTER_TRIGGER (0)
|
||||
#define DEFAULT_HIGH_VOLTAGE (0)
|
||||
#define DEFAULT_TIMING_MODE (AUTO_TIMING)
|
||||
#define DEFAULT_READOUT_C0 (144444448) // rdo_clk, 144 MHz
|
||||
#define DEFAULT_READOUT_C1 (288888896) // rdo_x2_clk, 288 MHz
|
||||
#define DEFAULT_READOUT_C1 (144444448) // rdo_x2_clk, 144 MHz
|
||||
#define DEFAULT_SYSTEM_C0 (144444448) // run_clk, 144 MHz
|
||||
#define DEFAULT_SYSTEM_C1 (72222224) // chip_clk, 72 MHz
|
||||
#define DEFAULT_SYSTEM_C2 (18055556) // sync_clk, 18 MHz
|
||||
@ -40,6 +45,7 @@
|
||||
|
||||
/* Firmware Definitions */
|
||||
#define IP_HEADER_SIZE (20)
|
||||
#define FIXED_PLL_FREQUENCY (020000000) // 20MHz
|
||||
#define READOUT_PLL_VCO_FREQ_HZ (866666688) // Hz
|
||||
#define SYSTEM_PLL_VCO_FREQ_HZ (722222240) // Hz
|
||||
|
||||
|
||||
@ -4,29 +4,38 @@
|
||||
#define REG_OFFSET (4)
|
||||
|
||||
/* Base addresses 0x1804 0000 ---------------------------------------------*/
|
||||
|
||||
/* Reconfiguration core for readout pll */
|
||||
#define BASE_READOUT_PLL (0x0000) // 0x1804_0000 - 0x1804_07FF
|
||||
|
||||
/* Reconfiguration core for system pll */
|
||||
#define BASE_SYSTEM_PLL (0x0800) // 0x1804_0800 - 0x1804_0FFF
|
||||
|
||||
/* Clock Generation */
|
||||
#define BASE_CLK_GENERATION (0x1000) // 0x1804_1000 - 0x1804_XXXX //TODO
|
||||
|
||||
/* Base addresses 0x1806 0000 ---------------------------------------------*/
|
||||
/* General purpose control and status registers */
|
||||
#define BASE_CONTROL (0x0000) // 0x1806_0000 - 0x1806_00FF https://git.psi.ch/sls_detectors_firmware/mythen_III_mcb/blob/master/code/hdl/ctrl/ctrl.vhd
|
||||
#define BASE_CONTROL (0x0000) // 0x1806_0000 - 0x1806_00FF
|
||||
// https://git.psi.ch/sls_detectors_firmware/mythen_III_mcb/blob/master/code/hdl/ctrl/ctrl.vhd
|
||||
|
||||
/* ASIC Control */
|
||||
#define BASE_ASIC (0x0100) // 0x1806_0100 - 0x1806_010F
|
||||
|
||||
/* ASIC Digital Interface. Data recovery core */
|
||||
#define BASE_ADIF (0x0110) // 0x1806_0110 - 0x1806_011F https://git.psi.ch/sls_detectors_firmware/vhdl_library/blob/2e81ccbdbc5cb81813ba190fbdba43e8d6884eb9/adif/adif_ctrl.vhd
|
||||
#define BASE_ADIF (0x0110) // 0x1806_0110 - 0x1806_011F
|
||||
// https://git.psi.ch/sls_detectors_firmware/vhdl_library/blob/2e81ccbdbc5cb81813ba190fbdba43e8d6884eb9/adif/adif_ctrl.vhd
|
||||
|
||||
/* Formatting of data core */
|
||||
#define BASE_FMT (0x0120) // 0x1806_0120 - 0x1806_012F
|
||||
|
||||
/* Pattern control and status registers */
|
||||
#define BASE_PATTERN_CONTROL (0x00200) // 0x1806_0200 - 0x1806_02FF https://git.psi.ch/sls_detectors_firmware/vhdl_library/blob/2e81ccbdbc5cb81813ba190fbdba43e8d6884eb9/pattern_flow/pattern_flow_ctrl.vhd
|
||||
#define BASE_PATTERN_CONTROL (0x00200) // 0x1806_0200 - 0x1806_02FF
|
||||
// https://git.psi.ch/sls_detectors_firmware/vhdl_library/blob/2e81ccbdbc5cb81813ba190fbdba43e8d6884eb9/pattern_flow/pattern_flow_ctrl.vhd
|
||||
|
||||
/* UDP datagram generator */
|
||||
#define BASE_UDP_RAM (0x01000) // 0x1806_1000 - 0x1806_1FFF
|
||||
|
||||
/* Pattern RAM. Pattern table */
|
||||
#define BASE_PATTERN_RAM (0x10000) // 0x1807_0000 - 0x1807_FFFF
|
||||
|
||||
@ -126,15 +135,15 @@
|
||||
#define PAT_STATUS_REG (0x00 * REG_OFFSET + BASE_PATTERN_CONTROL)
|
||||
#define PAT_STATUS_RUN_BUSY_OFST (0)
|
||||
#define PAT_STATUS_RUN_BUSY_MSK (0x00000001 << PAT_STATUS_RUN_BUSY_OFST)
|
||||
#define PAT_STATUS_WAIT_FOR_TRGGR_OFST (0)
|
||||
#define PAT_STATUS_WAIT_FOR_TRGGR_OFST (3)
|
||||
#define PAT_STATUS_WAIT_FOR_TRGGR_MSK (0x00000001 << PAT_STATUS_WAIT_FOR_TRGGR_OFST)
|
||||
#define PAT_STATUS_DLY_BFRE_TRGGR_OFST (0)
|
||||
#define PAT_STATUS_DLY_BFRE_TRGGR_OFST (4)
|
||||
#define PAT_STATUS_DLY_BFRE_TRGGR_MSK (0x00000001 << PAT_STATUS_DLY_BFRE_TRGGR_OFST)
|
||||
#define PAT_STATUS_FIFO_FULL_OFST (0)
|
||||
#define PAT_STATUS_FIFO_FULL_OFST (5)
|
||||
#define PAT_STATUS_FIFO_FULL_MSK (0x00000001 << PAT_STATUS_FIFO_FULL_OFST)
|
||||
#define PAT_STATUS_DLY_AFTR_TRGGR_OFST (0)
|
||||
#define PAT_STATUS_DLY_AFTR_TRGGR_OFST (15)
|
||||
#define PAT_STATUS_DLY_AFTR_TRGGR_MSK (0x00000001 << PAT_STATUS_DLY_AFTR_TRGGR_OFST)
|
||||
#define PAT_STATUS_CSM_BUSY_OFST (0)
|
||||
#define PAT_STATUS_CSM_BUSY_OFST (17)
|
||||
#define PAT_STATUS_CSM_BUSY_MSK (0x00000001 << PAT_STATUS_CSM_BUSY_OFST)
|
||||
|
||||
/* Delay left 64bit Register */
|
||||
@ -184,6 +193,9 @@
|
||||
/* External Signal register */
|
||||
#define EXT_SIGNAL_REG (0x30 * REG_OFFSET + BASE_PATTERN_CONTROL)
|
||||
|
||||
#define EXT_SIGNAL_OFST (0)
|
||||
#define EXT_SIGNAL_MSK (0x00000001 << EXT_SIGNAL_OFST)
|
||||
|
||||
/* Trigger Delay 64 bit register */
|
||||
#define SET_TRIGGER_DELAY_LSB_REG (0x32 * REG_OFFSET + BASE_PATTERN_CONTROL)
|
||||
#define SET_TRIGGER_DELAY_MSB_REG (0x33 * REG_OFFSET + BASE_PATTERN_CONTROL)
|
||||
|
||||
Binary file not shown.
@ -84,13 +84,10 @@ void basictests() {
|
||||
uint64_t macadd = getDetectorMAC();
|
||||
int64_t fwversion = getFirmwareVersion();
|
||||
int64_t swversion = getServerVersion();
|
||||
int64_t sw_fw_apiversion = 0;
|
||||
int64_t sw_fw_apiversion = getFirmwareAPIVersion();;
|
||||
int64_t client_sw_apiversion = getClientServerAPIVersion();
|
||||
uint32_t requiredFirmwareVersion = REQRD_FRMWRE_VRSN;
|
||||
|
||||
|
||||
if (fwversion >= MIN_REQRD_VRSN_T_RD_API)
|
||||
sw_fw_apiversion = getFirmwareAPIVersion();
|
||||
FILE_LOG(logINFOBLUE, ("*************************************************\n"
|
||||
"Hardware Version:\t\t 0x%x\n"
|
||||
|
||||
@ -609,7 +606,6 @@ int setDelayAfterTrigger(int64_t val) {
|
||||
|
||||
int64_t getDelayAfterTrigger() {
|
||||
return get64BitReg(SET_TRIGGER_DELAY_LSB_REG, SET_TRIGGER_DELAY_MSB_REG) / (1E-9 * FIXED_PLL_FREQUENCY);
|
||||
|
||||
}
|
||||
|
||||
int64_t getNumFramesLeft() {
|
||||
@ -706,10 +702,26 @@ int setHighVoltage(int val){
|
||||
|
||||
/* parameters - timing */
|
||||
void setTiming( enum timingMode arg){
|
||||
// to be implemented
|
||||
if(arg != GET_TIMING_MODE){
|
||||
switch((int)arg){
|
||||
case AUTO_TIMING:
|
||||
FILE_LOG(logINFO, ("Set Timing: Auto\n"));
|
||||
bus_w(EXT_SIGNAL_REG, bus_r(EXT_SIGNAL_REG) & ~EXT_SIGNAL_MSK);
|
||||
break;
|
||||
case TRIGGER_EXPOSURE:
|
||||
FILE_LOG(logINFO, ("Set Timing: Trigger\n"));
|
||||
bus_w(EXT_SIGNAL_REG, bus_r(EXT_SIGNAL_REG) | EXT_SIGNAL_MSK);
|
||||
break;
|
||||
default:
|
||||
FILE_LOG(logERROR, ("Unknown timing mode %d\n", arg));
|
||||
return;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
enum timingMode getTiming() {
|
||||
if (bus_r(EXT_SIGNAL_REG) == EXT_SIGNAL_MSK)
|
||||
return TRIGGER_EXPOSURE;
|
||||
return AUTO_TIMING;
|
||||
}
|
||||
|
||||
@ -1068,12 +1080,12 @@ int checkDetectorType() {
|
||||
}
|
||||
int type = atoi(buffer);
|
||||
if (type > TYPE_TOLERANCE) {
|
||||
FILE_LOG(logERROR, ("No Module attached! Expected %d for Mythen, got %d\n", TYPE_MYTHEN3_MODULE_VAL, type));
|
||||
FILE_LOG(logERROR, ("No Module attached! Expected %d for Mythen3, got %d\n", TYPE_MYTHEN3_MODULE_VAL, type));
|
||||
return -2;
|
||||
}
|
||||
|
||||
if (abs(type - TYPE_MYTHEN3_MODULE_VAL) > TYPE_TOLERANCE) {
|
||||
FILE_LOG(logERROR, ("Wrong Module attached! Expected %d for Mythen, got %d\n", TYPE_MYTHEN3_MODULE_VAL, type));
|
||||
FILE_LOG(logERROR, ("Wrong Module attached! Expected %d for Mythen3, got %d\n", TYPE_MYTHEN3_MODULE_VAL, type));
|
||||
return FAIL;
|
||||
}
|
||||
return OK;
|
||||
@ -1373,7 +1385,7 @@ int stopStateMachine(){
|
||||
#endif
|
||||
//stop state machine
|
||||
bus_w(CONTROL_REG, bus_r(CONTROL_REG) | CONTROL_STP_ACQSTN_MSK);
|
||||
FILE_LOG(logINFO, ("Status Register: %08x\n",bus_r(STATUS_REG)));
|
||||
FILE_LOG(logINFO, ("Status Register: %08x\n", bus_r(STATUS_REG)));
|
||||
return OK;
|
||||
}
|
||||
|
||||
@ -1430,7 +1442,7 @@ enum runStatus getRunStatus(){
|
||||
return s;
|
||||
}
|
||||
|
||||
void readFrame(int *ret, char *mess){
|
||||
void readFrame(int *ret, char *mess) {
|
||||
// wait for status to be done
|
||||
while(runBusy()){
|
||||
usleep(500);
|
||||
@ -1450,7 +1462,6 @@ void readFrame(int *ret, char *mess){
|
||||
} else {
|
||||
FILE_LOG(logINFOGREEN, ("Acquisition successfully finished\n"));
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
u_int32_t runBusy() {
|
||||
@ -1464,11 +1475,11 @@ u_int32_t runBusy() {
|
||||
|
||||
/* common */
|
||||
|
||||
int calculateDataBytes(){
|
||||
int calculateDataBytes() {
|
||||
return 0;
|
||||
}
|
||||
|
||||
int getTotalNumberOfChannels(){return ((int)getNumberOfChannelsPerChip() * (int)getNumberOfChips());}
|
||||
int getNumberOfChips(){return NCHIP;}
|
||||
int getNumberOfDACs(){return NDAC;}
|
||||
int getNumberOfChannelsPerChip(){return NCHAN;}
|
||||
int getTotalNumberOfChannels() {return ((int)getNumberOfChannelsPerChip() * (int)getNumberOfChips());}
|
||||
int getNumberOfChips() {return NCHIP;}
|
||||
int getNumberOfDACs() {return NDAC;}
|
||||
int getNumberOfChannelsPerChip() {return NCHAN;}
|
||||
|
||||
@ -2,7 +2,6 @@
|
||||
#include "sls_detector_defs.h"
|
||||
|
||||
#define REQRD_FRMWRE_VRSN 0x190000
|
||||
#define MIN_REQRD_VRSN_T_RD_API 0x190000
|
||||
|
||||
#define CTRL_SRVR_INIT_TIME_US (300 * 1000)
|
||||
|
||||
@ -45,7 +44,6 @@
|
||||
#define READOUT_PLL_VCO_FREQ_HZ (1250000000) // 1.25GHz
|
||||
#define SYSTEM_PLL_VCO_FREQ_HZ (1250000000) // 1.25GHz
|
||||
#define MAX_PATTERN_LENGTH (0x2000) // maximum number of words (64bit)
|
||||
#define WAIT_TIME_US_STP_ACQ (100)
|
||||
|
||||
/** Other Definitions */
|
||||
#define BIT16_MASK (0xFFFF)
|
||||
|
||||
@ -84,11 +84,10 @@ int updateDatabytesandAllocateRAM();
|
||||
void updateDataBytes();
|
||||
#endif
|
||||
|
||||
#if defined(GOTTHARDD) || defined(JUNGFRAUD) || defined(MYTHEN3D) || GOTTHARD2D
|
||||
#if defined(GOTTHARDD) || defined(JUNGFRAUD) || defined(MYTHEN3D)
|
||||
int setDefaultDacs();
|
||||
#endif
|
||||
#ifdef GOTTHARD2D
|
||||
int setDefaultOnChipDacs();
|
||||
int readConfigFile();
|
||||
#endif
|
||||
|
||||
@ -101,13 +100,13 @@ int readRegister(uint32_t offset, uint32_t* retval);
|
||||
uint32_t writeRegister16And32(uint32_t offset, uint32_t data); //FIXME its not there in ctb or moench?
|
||||
uint32_t readRegister16And32(uint32_t offset);
|
||||
#else
|
||||
extern u_int32_t writeRegister(u_int32_t offset, u_int32_t data); // blackfin.h
|
||||
extern u_int32_t readRegister(u_int32_t offset); // blackfin.h
|
||||
extern u_int32_t writeRegister(u_int32_t offset, u_int32_t data); // blackfin.h or nios.h
|
||||
extern u_int32_t readRegister(u_int32_t offset); // blackfin.h or nios.h
|
||||
#endif
|
||||
|
||||
|
||||
// firmware functions (resets)
|
||||
#if defined(JUNGFRAUD) || defined(CHIPTESTBOARDD) || defined(MOENCHD) || defined(MYTHEN3D)
|
||||
#if defined(JUNGFRAUD) || defined(CHIPTESTBOARDD) || defined(MOENCHD) || defined(MYTHEN3D) || defined(GOTTHARD2D)
|
||||
void cleanFifos();
|
||||
void resetCore();
|
||||
void resetPeripheral();
|
||||
@ -178,6 +177,20 @@ int setExpTime(int64_t val);
|
||||
int64_t getExpTime();
|
||||
int setPeriod(int64_t val);
|
||||
int64_t getPeriod();
|
||||
#ifdef GOTTHARD2D
|
||||
void setNumFramesBurst(int64_t val);
|
||||
int64_t getNumFramesBurst();
|
||||
void setNumFramesCont(int64_t val);
|
||||
int64_t getNumFramesCont();
|
||||
int setExptimeBurst(int64_t val);
|
||||
int setExptimeCont(int64_t val);
|
||||
int setExptimeBoth(int64_t val);
|
||||
int64_t getExptimeBoth();
|
||||
int setPeriodBurst(int64_t val);
|
||||
int64_t getPeriodBurst();
|
||||
int setPeriodCont(int64_t val);
|
||||
int64_t getPeriodCont();
|
||||
#endif
|
||||
#ifdef EIGERD
|
||||
int setSubExpTime(int64_t val);
|
||||
int64_t getSubExpTime();
|
||||
@ -203,22 +216,18 @@ void setCounterMask(uint32_t arg);
|
||||
uint32_t getCounterMask();
|
||||
#endif
|
||||
|
||||
#if defined(JUNGFRAUD) || defined(GOTTHARDD) || defined(CHIPTESTBOARDD) || defined(MOENCHD) || defined(MYTHEN3D)
|
||||
#if defined(JUNGFRAUD) || defined(GOTTHARDD) || defined(CHIPTESTBOARDD) || defined(MOENCHD) || defined(MYTHEN3D) || defined(GOTTHARD2D)
|
||||
int setDelayAfterTrigger(int64_t val);
|
||||
int64_t getDelayAfterTrigger();
|
||||
#endif
|
||||
#if defined(JUNGFRAUD) || defined(GOTTHARDD) || defined(CHIPTESTBOARDD) || defined(MOENCHD) || defined(MYTHEN3D) || defined(GOTTHARD2D)
|
||||
int64_t getNumFramesLeft();
|
||||
int64_t getNumTriggersLeft();
|
||||
#endif
|
||||
#if defined(JUNGFRAUD) || defined(GOTTHARDD) || defined(CHIPTESTBOARDD) || defined(MOENCHD) || defined(MYTHEN3D)
|
||||
int64_t getDelayAfterTriggerLeft();
|
||||
int64_t getPeriodLeft();
|
||||
#endif
|
||||
#ifdef GOTTHARDD
|
||||
int64_t getExpTimeLeft();
|
||||
#endif
|
||||
#if defined(JUNGFRAUD) || defined(CHIPTESTBOARDD) || defined(MOENCHD) || defined(MYTHEN3D)
|
||||
#if defined(JUNGFRAUD) || defined(CHIPTESTBOARDD) || defined(MOENCHD) || defined(MYTHEN3D) || defined(GOTTHARD2D)
|
||||
int64_t getFramesFromStart();
|
||||
int64_t getActualTime();
|
||||
int64_t getMeasurementTime();
|
||||
@ -293,10 +302,8 @@ int setHighVoltage(int val);
|
||||
|
||||
|
||||
// parameters - timing, extsig
|
||||
#if !defined(GOTTHARD2D)
|
||||
void setTiming( enum timingMode arg);
|
||||
enum timingMode getTiming();
|
||||
#endif
|
||||
#ifdef GOTTHARDD
|
||||
void setExtSignal(enum externalSignalFlag mode);
|
||||
int getExtSignal();
|
||||
@ -324,7 +331,6 @@ int getAdcConfigured();
|
||||
int configureMAC();
|
||||
int setDetectorPosition(int pos[]);
|
||||
int* getDetectorPosition();
|
||||
int isConfigurable();
|
||||
|
||||
|
||||
#ifdef EIGERD
|
||||
@ -443,6 +449,8 @@ int setClockDivider(enum CLKINDEX ind, int val);
|
||||
int getClockDivider(enum CLKINDEX ind);
|
||||
|
||||
#elif GOTTHARD2D
|
||||
int checkDetectorType();
|
||||
int powerChip (int on);
|
||||
int setPhase(enum CLKINDEX ind, int val, int degrees);
|
||||
int getPhase(enum CLKINDEX ind, int degrees);
|
||||
int getMaxPhase(enum CLKINDEX ind);
|
||||
@ -485,6 +493,9 @@ int setTransmissionDelayRight(int value);
|
||||
|
||||
|
||||
// aquisition
|
||||
#ifdef GOTTHARD2D
|
||||
int updateAcquisitionRegisters(char* mess);
|
||||
#endif
|
||||
#ifdef EIGERD
|
||||
int prepareAcquisition();
|
||||
#endif
|
||||
|
||||
@ -199,7 +199,7 @@ int set_inject_channel(int);
|
||||
int get_inject_channel(int);
|
||||
int set_veto_photon(int);
|
||||
int get_veto_photon(int);
|
||||
int set_veto_refernce(int);
|
||||
int set_veto_reference(int);
|
||||
int get_burst_mode(int);
|
||||
int set_burst_mode(int);
|
||||
int set_adc_enable_mask_10g(int);
|
||||
|
||||
@ -87,13 +87,9 @@ void ALTERA_PLL_C10_Reconfigure(int pllIndex) {
|
||||
void ALTERA_PLL_C10_ResetPLL (int pllIndex) {
|
||||
uint32_t resetreg = ALTERA_PLL_C10_Reset_Reg[pllIndex];
|
||||
uint32_t resetmsk = ALTERA_PLL_C10_Reset_Msk[pllIndex];
|
||||
|
||||
#ifdef MYTHEN3D
|
||||
FILE_LOG(logINFO, ("Resetting PLL %d\n", pllIndex));
|
||||
bus_w_csp1(resetreg, bus_r_csp1(resetreg) | resetmsk);
|
||||
#else
|
||||
FILE_LOG(logWARNING, ("Resetting PLL %d not implemented!\n", pllIndex));
|
||||
#endif
|
||||
|
||||
usleep(ALTERA_PLL_C10_WAIT_TIME_US);
|
||||
}
|
||||
|
||||
|
||||
@ -484,7 +484,7 @@ void function_table() {
|
||||
flist[F_GET_INJECT_CHANNEL] = &get_inject_channel;
|
||||
flist[F_SET_VETO_PHOTON] = &set_veto_photon;
|
||||
flist[F_GET_VETO_PHOTON] = &get_veto_photon;
|
||||
flist[F_SET_VETO_REFERENCE] = &set_veto_refernce;
|
||||
flist[F_SET_VETO_REFERENCE] = &set_veto_reference;
|
||||
flist[F_GET_BURST_MODE] = &get_burst_mode;
|
||||
flist[F_SET_BURST_MODE] = &set_burst_mode;
|
||||
flist[F_SET_ADC_ENABLE_MASK_10G] = &set_adc_enable_mask_10g;
|
||||
@ -685,10 +685,6 @@ int set_timing_mode(int file_des) {
|
||||
return printSocketReadError();
|
||||
FILE_LOG(logDEBUG1, ("Setting external communication mode to %d\n", arg));
|
||||
|
||||
#ifdef GOTTHARD2D
|
||||
functionNotImplemented();
|
||||
#else
|
||||
|
||||
// set
|
||||
if ((arg != GET_TIMING_MODE) && (Server_VerifyLock() == OK)) {
|
||||
switch (arg) {
|
||||
@ -709,7 +705,6 @@ int set_timing_mode(int file_des) {
|
||||
retval = getTiming();
|
||||
validate((int)arg, (int)retval, "set timing mode", DEC);
|
||||
FILE_LOG(logDEBUG1, ("Timing Mode: %d\n",retval));
|
||||
#endif
|
||||
|
||||
return Server_SendResult(file_des, INT32, UPDATE, &retval, sizeof(retval));
|
||||
}
|
||||
@ -1782,6 +1777,12 @@ int start_acquisition(int file_des) {
|
||||
FILE_LOG(logERROR,(mess));
|
||||
}
|
||||
else
|
||||
#endif
|
||||
#ifdef GOTTHARD2D
|
||||
if (updateAcquisitionRegisters(mess) == FAIL) {
|
||||
ret = FAIL;
|
||||
}
|
||||
else
|
||||
#endif
|
||||
if (configured == FAIL) {
|
||||
ret = FAIL;
|
||||
@ -1792,12 +1793,8 @@ int start_acquisition(int file_des) {
|
||||
if (ret == FAIL) {
|
||||
#if defined(CHIPTESTBOARDD) || defined(MOENCHD) || defined(VIRTUAL)
|
||||
sprintf(mess, "Could not start acquisition. Could not create udp socket in server. Check udp_dstip & udp_dstport.\n");
|
||||
#else
|
||||
#if defined(GOTTHARD2D)
|
||||
sprintf(mess, "Could not start acquisition due to #frames > %d in burst mode\n", MAX_FRAMES_IN_BURST_MODE);
|
||||
#else
|
||||
sprintf(mess, "Could not start acquisition\n");
|
||||
#endif
|
||||
#endif
|
||||
FILE_LOG(logERROR,(mess));
|
||||
}
|
||||
@ -1916,6 +1913,12 @@ int start_and_read_all(int file_des) {
|
||||
FILE_LOG(logERROR,(mess));
|
||||
}
|
||||
else
|
||||
#endif
|
||||
#ifdef GOTTHARD2D
|
||||
if (updateAcquisitionRegisters(mess) == FAIL) {
|
||||
ret = FAIL;
|
||||
}
|
||||
else
|
||||
#endif
|
||||
if (configured == FAIL) {
|
||||
ret = FAIL;
|
||||
@ -1926,12 +1929,8 @@ int start_and_read_all(int file_des) {
|
||||
if (ret == FAIL) {
|
||||
#if defined(VIRTUAL) || defined(CHIPTESTBOARDD) || defined(MOENCHD)
|
||||
sprintf(mess, "Could not start acquisition. Could not create udp socket in server. Check udp_dstip & udp_dstport.\n");
|
||||
#else
|
||||
#if defined(GOTTHARD2D)
|
||||
sprintf(mess, "Could not start acquisition due to #frames > %d in burst mode\n", MAX_FRAMES_IN_BURST_MODE);
|
||||
#else
|
||||
sprintf(mess, "Could not start acquisition\n");
|
||||
#endif
|
||||
#endif
|
||||
FILE_LOG(logERROR,(mess));
|
||||
}
|
||||
@ -2225,7 +2224,7 @@ int get_delay_after_trigger(int file_des) {
|
||||
memset(mess, 0, sizeof(mess));
|
||||
int64_t retval = -1;
|
||||
|
||||
#if !defined(JUNGFRAUD) && !defined(GOTTHARDD) && !defined(CHIPTESTBOARDD) && !defined(MOENCHD) && !defined(MYTHEN3D)
|
||||
#if !defined(JUNGFRAUD) && !defined(GOTTHARDD) && !defined(CHIPTESTBOARDD) && !defined(MOENCHD) && !defined(MYTHEN3D) && !defined(GOTTHARD2D)
|
||||
functionNotImplemented();
|
||||
#else
|
||||
// get only
|
||||
@ -2244,7 +2243,7 @@ int set_delay_after_trigger(int file_des) {
|
||||
return printSocketReadError();
|
||||
FILE_LOG(logDEBUG1, ("Setting delay after trigger %lld ns\n", (long long int)arg));
|
||||
|
||||
#if !defined(JUNGFRAUD) && !defined(GOTTHARDD) && !defined(CHIPTESTBOARDD) && !defined(MOENCHD) && !defined(MYTHEN3D)
|
||||
#if !defined(JUNGFRAUD) && !defined(GOTTHARDD) && !defined(CHIPTESTBOARDD) && !defined(MOENCHD) && !defined(MYTHEN3D) && !defined(GOTTHARD2D)
|
||||
functionNotImplemented();
|
||||
#else
|
||||
// only set
|
||||
@ -2458,7 +2457,7 @@ int get_period_left(int file_des) {
|
||||
memset(mess, 0, sizeof(mess));
|
||||
int64_t retval = -1;
|
||||
|
||||
#if !defined(JUNGFRAUD) && !defined(GOTTHARDD) && !defined(CHIPTESTBOARDD) && !defined(MOENCHD) && !defined(MYTHEN3D)
|
||||
#if !defined(JUNGFRAUD) && !defined(GOTTHARDD) && !defined(CHIPTESTBOARDD) && !defined(MOENCHD) && !defined(MYTHEN3D) && !defined(GOTTHARD2D)
|
||||
functionNotImplemented();
|
||||
#else
|
||||
// get only
|
||||
@ -2473,7 +2472,7 @@ int get_delay_after_trigger_left(int file_des) {
|
||||
memset(mess, 0, sizeof(mess));
|
||||
int64_t retval = -1;
|
||||
|
||||
#if !defined(JUNGFRAUD) && !defined(GOTTHARDD) && !defined(CHIPTESTBOARDD) && !defined(MOENCHD) && !defined(MYTHEN3D)
|
||||
#if !defined(JUNGFRAUD) && !defined(GOTTHARDD) && !defined(CHIPTESTBOARDD) && !defined(MOENCHD) && !defined(MYTHEN3D) && !defined(GOTTHARD2D)
|
||||
functionNotImplemented();
|
||||
#else
|
||||
// get only
|
||||
@ -2518,7 +2517,7 @@ int get_frames_from_start(int file_des) {
|
||||
memset(mess, 0, sizeof(mess));
|
||||
int64_t retval = -1;
|
||||
|
||||
#if !defined(JUNGFRAUD) && !defined(CHIPTESTBOARDD) && !defined(MOENCHD) && !defined(MYTHEN3D)
|
||||
#if !defined(JUNGFRAUD) && !defined(CHIPTESTBOARDD) && !defined(MOENCHD) && !defined(MYTHEN3D) && !defined(GOTTHARD2D)
|
||||
functionNotImplemented();
|
||||
#else
|
||||
// get only
|
||||
@ -2533,7 +2532,7 @@ int get_actual_time(int file_des) {
|
||||
memset(mess, 0, sizeof(mess));
|
||||
int64_t retval = -1;
|
||||
|
||||
#if !defined(JUNGFRAUD) && !defined(CHIPTESTBOARDD) && !defined(MOENCHD) && !defined(MYTHEN3D)
|
||||
#if !defined(JUNGFRAUD) && !defined(CHIPTESTBOARDD) && !defined(MOENCHD) && !defined(MYTHEN3D) && !defined(GOTTHARD2D)
|
||||
functionNotImplemented();
|
||||
#else
|
||||
// get only
|
||||
@ -2548,7 +2547,7 @@ int get_measurement_time(int file_des) {
|
||||
memset(mess, 0, sizeof(mess));
|
||||
int64_t retval = -1;
|
||||
|
||||
#if !defined(JUNGFRAUD) && !defined(CHIPTESTBOARDD) && !defined(MOENCHD) && !defined(MYTHEN3D)
|
||||
#if !defined(JUNGFRAUD) && !defined(CHIPTESTBOARDD) && !defined(MOENCHD) && !defined(MYTHEN3D) && !defined(GOTTHARD2D)
|
||||
functionNotImplemented();
|
||||
#else
|
||||
// get only
|
||||
@ -3836,12 +3835,12 @@ int power_chip(int file_des) {
|
||||
return printSocketReadError();
|
||||
FILE_LOG(logDEBUG1, ("Powering chip to %d\n", arg));
|
||||
|
||||
#if (!defined(JUNGFRAUD)) && (!defined(MOENCHD)) && (!defined(MYTHEN3D))
|
||||
#if !defined(JUNGFRAUD) && !defined(MOENCHD) && !defined(MYTHEN3D) && !defined(GOTTHARD2D)
|
||||
functionNotImplemented();
|
||||
#else
|
||||
// set & get
|
||||
if ((arg == -1) || (Server_VerifyLock() == OK)) {
|
||||
#ifdef MYTHEN3D
|
||||
#if defined(MYTHEN3D) || defined(GOTTHARD2D)
|
||||
// check only when powering on
|
||||
if (arg != -1 && arg != 0) {
|
||||
int type_ret = checkDetectorType();
|
||||
@ -6446,7 +6445,7 @@ int get_veto_photon(int file_des) {
|
||||
}
|
||||
|
||||
|
||||
int set_veto_refernce(int file_des) {
|
||||
int set_veto_reference(int file_des) {
|
||||
ret = OK;
|
||||
memset(mess, 0, sizeof(mess));
|
||||
int args[2] = {-1, -1};
|
||||
|
||||
@ -152,10 +152,10 @@ class Detector {
|
||||
|
||||
void setPeriod(ns t, Positions pos = {});
|
||||
|
||||
/** [Gotthard][Jungfrau][CTB][Mythen3] */
|
||||
/** [Gotthard][Jungfrau][CTB][Mythen3][Gotthard2] */
|
||||
Result<ns> getDelayAfterTrigger(Positions pos = {}) const;
|
||||
|
||||
/** [Gotthard][Jungfrau][CTB][Mythen3] */
|
||||
/** [Gotthard][Jungfrau][CTB][Mythen3][Gotthard2] */
|
||||
void setDelayAfterTrigger(ns value, Positions pos = {});
|
||||
|
||||
/** [Gotthard][Jungfrau][CTB][Mythen3][Gotthard2] */
|
||||
@ -164,10 +164,10 @@ class Detector {
|
||||
/** [Gotthard][Jungfrau][CTB][Mythen3][Gotthard2] */
|
||||
Result<int64_t> getNumberOfTriggersLeft(Positions pos = {}) const;
|
||||
|
||||
/** [Gotthard][Jungfrau][CTB] */
|
||||
/** [Gotthard][Jungfrau][CTB][Mythen3][Gotthard2] */
|
||||
Result<ns> getDelayAfterTriggerLeft(Positions pos = {}) const;
|
||||
|
||||
/** [Gotthard][Jungfrau][CTB] */
|
||||
/** [Gotthard][Jungfrau][CTB][Mythen3][Gotthard2] */
|
||||
Result<ns> getPeriodLeft(Positions pos = {}) const;
|
||||
|
||||
Result<defs::timingMode> getTimingMode(Positions pos = {}) const;
|
||||
@ -200,45 +200,45 @@ class Detector {
|
||||
/** [Gotthard][Jungfrau][CTB] */
|
||||
void setADCPhaseInDegrees(int value, Positions pos = {});
|
||||
|
||||
/** [Gotthard2] Hz */
|
||||
/** [Mythen3][Gotthard2] Hz */
|
||||
Result<int> getClockFrequency(int clkIndex, Positions pos = {});
|
||||
|
||||
/** [not implemented] Hz */
|
||||
void setClockFrequency(int clkIndex, int value, Positions pos = {});
|
||||
|
||||
/** [Gotthard2] */
|
||||
/** [Mythen3][Gotthard2] */
|
||||
Result<int> getClockPhase(int clkIndex, Positions pos = {});
|
||||
|
||||
/** [Gotthard2] */
|
||||
/** [Mythen3][Gotthard2] */
|
||||
void setClockPhase(int clkIndex, int value, Positions pos = {});
|
||||
|
||||
/** [Gotthard2] */
|
||||
/** [Mythen3][Gotthard2] */
|
||||
Result<int> getMaxClockPhaseShift(int clkIndex, Positions pos = {});
|
||||
|
||||
/** [Gotthard2] */
|
||||
/** [Mythen3][Gotthard2] */
|
||||
Result<int> getClockPhaseinDegrees(int clkIndex, Positions pos = {});
|
||||
|
||||
/** [Gotthard2] */
|
||||
/** [Mythen3][Gotthard2] */
|
||||
void setClockPhaseinDegrees(int clkIndex, int value, Positions pos = {});
|
||||
|
||||
/** [Gotthard2] */
|
||||
/** [Mythen3][Gotthard2] */
|
||||
Result<int> getClockDivider(int clkIndex, Positions pos = {});
|
||||
|
||||
/** [Gotthard2] */
|
||||
/** [Mythen3][Gotthard2] */
|
||||
void setClockDivider(int clkIndex, int value, Positions pos = {});
|
||||
|
||||
Result<int> getHighVoltage(Positions pos = {}) const;
|
||||
|
||||
/** [Jungfrau][Mythen3] */
|
||||
/** [Jungfrau][Mythen3][Gotthard2] */
|
||||
Result<bool> getPowerChip(Positions pos = {}) const;
|
||||
|
||||
/** [Jungfrau][Mythen3] */
|
||||
/** [Jungfrau][Mythen3][Gotthard2] */
|
||||
void setPowerChip(bool on, Positions pos = {});
|
||||
|
||||
/**
|
||||
* [Gotthard Options: 0, 90, 110, 120, 150, 180, 200]
|
||||
* [Jungfrau, CTB Options: 0, 60 - 200]
|
||||
* [Eiger Options: 0 - 200]
|
||||
* [Gotthard] Options: 0, 90, 110, 120, 150, 180, 200
|
||||
* [Jungfrau], CTB Options: 0, 60 - 200
|
||||
* [Eiger][Mythen3][Gotthard2] Options: 0 - 200
|
||||
*/
|
||||
void setHighVoltage(int value, Positions pos = {});
|
||||
|
||||
@ -1100,40 +1100,40 @@ class Detector {
|
||||
/** [CTB] */
|
||||
void setPatternClockControl(uint64_t word, Positions pos = {});
|
||||
|
||||
/** [CTB] same as executing */
|
||||
/** [Mythen3][CTB] same as executing for CTB */
|
||||
Result<uint64_t> getPatternWord(int addr, Positions pos = {});
|
||||
|
||||
/** [CTB] Caution: If word is -1 reads the addr (same as
|
||||
/** [Mythen3][CTB] Caution: If word is -1 reads the addr (same as
|
||||
* executing the pattern) */
|
||||
void setPatternWord(int addr, uint64_t word, Positions pos = {});
|
||||
|
||||
/**[CTB] Options: level: -1 (complete pattern) and 0-2 levels
|
||||
/** [Mythen3][CTB] Options: level: -1 (complete pattern) and 0-2 levels
|
||||
* @returns array of start address and stop address
|
||||
*/
|
||||
Result<std::array<int, 2>> getPatternLoopAddresses(int level,
|
||||
Positions pos = {}) const;
|
||||
|
||||
/** [CTB] Options: level: -1 (complete pattern) and 0-2 levels */
|
||||
/** [Mythen3][CTB] Options: level: -1 (complete pattern) and 0-2 levels */
|
||||
void setPatternLoopAddresses(int level, int start, int stop, Positions pos = {});
|
||||
|
||||
/**[CTB] Options: level: -1 (complete pattern) and 0-2 levels
|
||||
/** [Mythen3][CTB] Options: level: -1 (complete pattern) and 0-2 levels
|
||||
* @returns number of loops
|
||||
*/
|
||||
Result<int> getPatternLoopCycles(int level, Positions pos = {}) const;
|
||||
|
||||
/** [CTB] n: 0-2, level: -1 (complete pattern) and 0-2 levels */
|
||||
/** [Mythen3][CTB] n: 0-2, level: -1 (complete pattern) and 0-2 levels */
|
||||
void setPatternLoopCycles(int level, int n, Positions pos = {});
|
||||
|
||||
/* [CTB] */
|
||||
/* [Mythen3][CTB] */
|
||||
Result<int> getPatternWaitAddr(int level, Positions pos = {}) const;
|
||||
|
||||
/** [CTB] Options: level 0-2 */
|
||||
/** [Mythen3][CTB] Options: level 0-2 */
|
||||
void setPatternWaitAddr(int level, int addr, Positions pos = {});
|
||||
|
||||
/** [CTB] */
|
||||
/** [Mythen3][CTB] */
|
||||
Result<uint64_t> getPatternWaitTime(int level, Positions pos = {}) const;
|
||||
|
||||
/** [CTB] Options: level 0-2 */
|
||||
/** [Mythen3][CTB] Options: level 0-2 */
|
||||
void setPatternWaitTime(int level, uint64_t t, Positions pos = {});
|
||||
|
||||
/** [CTB] */
|
||||
@ -1243,10 +1243,10 @@ class Detector {
|
||||
|
||||
void clearBit(uint32_t addr, int bitnr, Positions pos = {});
|
||||
|
||||
/** [Gotthard][Jungfrau][CTB] */
|
||||
/** [Gotthard][Jungfrau][Mythen3][Gotthard2][CTB] */
|
||||
void executeFirmwareTest(Positions pos = {});
|
||||
|
||||
/** [Gotthard][Jungfrau][CTB] */
|
||||
/** [Gotthard][Jungfrau][Mythen3][Gotthard2][CTB] */
|
||||
void executeBusTest(Positions pos = {});
|
||||
|
||||
/** [Gotthard][Jungfrau][CTB] not possible to read back*/
|
||||
@ -1280,13 +1280,13 @@ class Detector {
|
||||
/** Execute a command on the detector server console */
|
||||
void executeCommand(const std::string &value, Positions pos = {});
|
||||
|
||||
/** [Jungfrau][CTB] */
|
||||
/** [Jungfrau][Mythen3][Gotthard2][CTB] */
|
||||
Result<int64_t> getNumberOfFramesFromStart(Positions pos = {}) const;
|
||||
|
||||
/** [Jungfrau][CTB] Get time from detector start */
|
||||
/** [Jungfrau][Mythen3][Gotthard2][CTB] Get time from detector start */
|
||||
Result<ns> getActualTime(Positions pos = {}) const;
|
||||
|
||||
/** [Jungfrau][CTB] Get timestamp at a frame start */
|
||||
/** [Jungfrau][Mythen3][Gotthard2][CTB] Get timestamp at a frame start */
|
||||
Result<ns> getMeasurementTime(Positions pos = {}) const;
|
||||
|
||||
std::string getUserDetails() const;
|
||||
|
||||
@ -1455,7 +1455,7 @@ std::string CmdProxy::Pattern(int action) {
|
||||
std::ostringstream os;
|
||||
os << cmd << ' ';
|
||||
if (action == defs::HELP_ACTION) {
|
||||
os << "[fname]\n\t[Ctb] Loads binary pattern file with only pattern "
|
||||
os << "[fname]\n\t[Mythen3][Ctb] Loads binary pattern file with only pattern "
|
||||
"words"
|
||||
<< '\n';
|
||||
} else if (action == defs::GET_ACTION) {
|
||||
@ -1476,7 +1476,7 @@ std::string CmdProxy::PatternWord(int action) {
|
||||
std::ostringstream os;
|
||||
os << cmd << ' ';
|
||||
if (action == defs::HELP_ACTION) {
|
||||
os << "[step or address] [64 bit mask]\n\t[Ctb] 64 bit pattern at "
|
||||
os << "[step or address] [64 bit mask]\n\t[Mythen3][Ctb] 64 bit pattern at "
|
||||
"address of pattern memory."
|
||||
<< '\n';
|
||||
} else if (action == defs::GET_ACTION) {
|
||||
@ -1502,17 +1502,17 @@ std::string CmdProxy::PatternLoopAddresses(int action) {
|
||||
os << cmd << ' ';
|
||||
if (action == defs::HELP_ACTION) {
|
||||
if (cmd == "patlimits") {
|
||||
os << "[start addr] [stop addr] \n\t[Ctb] Limits of complete "
|
||||
os << "[start addr] [stop addr] \n\t[Mythen3][Ctb] Limits of complete "
|
||||
"pattern."
|
||||
<< '\n';
|
||||
} else if (cmd == "patloop0") {
|
||||
os << "[start addr] [stop addr] \n\t[Ctb] Limits of loop 0."
|
||||
os << "[start addr] [stop addr] \n\t[Mythen3][Ctb] Limits of loop 0."
|
||||
<< '\n';
|
||||
} else if (cmd == "patloop1") {
|
||||
os << "[start addr] [stop addr] \n\t[Ctb] Limits of loop 1."
|
||||
os << "[start addr] [stop addr] \n\t[Mythen3][Ctb] Limits of loop 1."
|
||||
<< '\n';
|
||||
} else if (cmd == "patloop2") {
|
||||
os << "[start addr] [stop addr] \n\t[Ctb] Limits of loop 2."
|
||||
os << "[start addr] [stop addr] \n\t[Mythen3][Ctb] Limits of loop 2."
|
||||
<< '\n';
|
||||
} else {
|
||||
throw sls::RuntimeError(
|
||||
@ -1557,11 +1557,11 @@ std::string CmdProxy::PatternLoopCycles(int action) {
|
||||
os << cmd << ' ';
|
||||
if (action == defs::HELP_ACTION) {
|
||||
if (cmd == "patnloop0") {
|
||||
os << "[n_cycles] \n\t[Ctb] Number of cycles of loop 0." << '\n';
|
||||
os << "[n_cycles] \n\t[Mythen3][Ctb] Number of cycles of loop 0." << '\n';
|
||||
} else if (cmd == "patnloop1") {
|
||||
os << "[n_cycles] \n\t[Ctb] Number of cycles of loop 1." << '\n';
|
||||
os << "[n_cycles] \n\t[Mythen3][Ctb] Number of cycles of loop 1." << '\n';
|
||||
} else if (cmd == "patnloop2") {
|
||||
os << "[n_cycles] \n\t[Ctb] Number of cycles of loop 2." << '\n';
|
||||
os << "[n_cycles] \n\t[Mythen3][Ctb] Number of cycles of loop 2." << '\n';
|
||||
} else {
|
||||
throw sls::RuntimeError(
|
||||
"Unknown command, use list to list all commands");
|
||||
@ -1602,11 +1602,11 @@ std::string CmdProxy::PatternWaitAddress(int action) {
|
||||
os << cmd << ' ';
|
||||
if (action == defs::HELP_ACTION) {
|
||||
if (cmd == "patwait0") {
|
||||
os << "[addr] \n\t[Ctb] Wait 0 address." << '\n';
|
||||
os << "[addr] \n\t[Mythen3][Ctb] Wait 0 address." << '\n';
|
||||
} else if (cmd == "patwait1") {
|
||||
os << "[addr] \n\t[Ctb] Wait 1 address." << '\n';
|
||||
os << "[addr] \n\t[Mythen3][Ctb] Wait 1 address." << '\n';
|
||||
} else if (cmd == "patwait2") {
|
||||
os << "[addr] \n\t[Ctb] Wait 2 address." << '\n';
|
||||
os << "[addr] \n\t[Mythen3][Ctb] Wait 2 address." << '\n';
|
||||
} else {
|
||||
throw sls::RuntimeError(
|
||||
"Unknown command, use list to list all commands");
|
||||
@ -1647,11 +1647,11 @@ std::string CmdProxy::PatternWaitTime(int action) {
|
||||
os << cmd << ' ';
|
||||
if (action == defs::HELP_ACTION) {
|
||||
if (cmd == "patwaittime0") {
|
||||
os << "[n_clk] \n\t[Ctb] Wait 0 time in clock cycles." << '\n';
|
||||
os << "[n_clk] \n\t[Mythen3][Ctb] Wait 0 time in clock cycles." << '\n';
|
||||
} else if (cmd == "patwaittime1") {
|
||||
os << "[n_clk] \n\t[Ctb] Wait 1 time in clock cycles." << '\n';
|
||||
os << "[n_clk] \n\t[Mythen3][Ctb] Wait 1 time in clock cycles." << '\n';
|
||||
} else if (cmd == "patwaittime2") {
|
||||
os << "[n_clk] \n\t[Ctb] Wait 2 time in clock cycles." << '\n';
|
||||
os << "[n_clk] \n\t[Mythen3][Ctb] Wait 2 time in clock cycles." << '\n';
|
||||
} else {
|
||||
throw sls::RuntimeError(
|
||||
"Unknown command, use list to list all commands");
|
||||
|
||||
@ -1003,47 +1003,54 @@ class CmdProxy {
|
||||
|
||||
INTEGER_COMMAND_NOID(frames, getNumberOfFrames, setNumberOfFrames,
|
||||
std::stol,
|
||||
"[n_frames]\n\tNumber of frames per aquire. In trigger mode, number of frames per trigger.");
|
||||
"[n_frames]\n\tNumber of frames per aquire. In trigger mode, number of frames per trigger."
|
||||
"\n\t[Gotthard2] Burst mode has a maximum of 2720 frames. Frames number for both modes are uploaded to detector just before acquisition starts");
|
||||
|
||||
INTEGER_COMMAND_NOID(triggers, getNumberOfTriggers, setNumberOfTriggers,
|
||||
std::stol,
|
||||
"[n_triggers]\n\tNumber of triggers per aquire. Use timing command to set timing mode.");
|
||||
|
||||
TIME_COMMAND(exptime, getExptime, setExptime,
|
||||
"[duration] [(optional unit) ns|us|ms|s]\n\tExposure time");
|
||||
"[duration] [(optional unit) ns|us|ms|s]\n\tExposure time"
|
||||
"\n\t[Gotthard2] Uploaded to detector just before acquisition starts");
|
||||
|
||||
TIME_COMMAND(period, getPeriod, setPeriod,
|
||||
"[duration] [(optional unit) ns|us|ms|s]\n\tPeriod between frames");
|
||||
"[duration] [(optional unit) ns|us|ms|s]\n\tPeriod between frames"
|
||||
"\n\t[Gotthard2] Uploaded to detector just before acquisition starts");
|
||||
|
||||
TIME_COMMAND(delay, getDelayAfterTrigger, setDelayAfterTrigger,
|
||||
"[duration] [(optional unit) ns|us|ms|s]\n\t[Jungfrau][Gotthard][Ctb][Mythen3] Delay after trigger");
|
||||
"[duration] [(optional unit) ns|us|ms|s]\n\t[Jungfrau][Gotthard][Mythen3][Gotthard2][Ctb] Delay after trigger");
|
||||
|
||||
GET_COMMAND(framesl, getNumberOfFramesLeft,
|
||||
"\n\t[Gotthard][Jungfrau][CTB][Mythen3][Gotthard2] Number of frames left in acquisition.");
|
||||
"\n\t[Gotthard][Jungfrau][Mythen3][Gotthard2][CTB] Number of frames left in acquisition.");
|
||||
|
||||
GET_COMMAND(triggersl, getNumberOfTriggersLeft,
|
||||
"\n\t[Gotthard][Jungfrau][CTB][Mythen3][Gotthard2] Number of triggers left in acquisition.");
|
||||
"\n\t[Gotthard][Jungfrau][Mythen3][Gotthard2][CTB] Number of triggers left in acquisition.");
|
||||
|
||||
TIME_GET_COMMAND(delayl, getDelayAfterTriggerLeft,
|
||||
"\n\t[Gotthard][Jungfrau][CTB] DelayLeft Delay Left in Acquisition.");
|
||||
"\n\t[Gotthard][Jungfrau][Mythen3][Gotthard2][CTB] DelayLeft Delay Left in Acquisition.");
|
||||
|
||||
TIME_GET_COMMAND(periodl, getPeriodLeft,
|
||||
"\n\t[Gotthard][Jungfrau][CTB] Period left for current frame.");
|
||||
"\n\t[Gotthard][Jungfrau][Mythen3][Gotthard2][CTB] Period left for current frame.");
|
||||
|
||||
INTEGER_COMMAND(timing, getTimingMode, setTimingMode, sls::StringTo<slsDetectorDefs::timingMode>,
|
||||
"[auto|trigger|gating|burst_trigger]\n\tTiming Mode of detector.\n\t[Jungfrau][Gotthard][Ctb] [auto|trigger]\n\t[Eiger] [auto|trigger|gating|burst_trigger]");
|
||||
"[auto|trigger|gating|burst_trigger]\n\tTiming Mode of detector.\n\t[Jungfrau][Gotthard][Mythen3][Gotthard2][Ctb] [auto|trigger]\n\t[Eiger] [auto|trigger|gating|burst_trigger]");
|
||||
|
||||
GET_COMMAND(maxadcphaseshift, getMaxADCPhaseShift,
|
||||
"\n\t[Jungfrau][CTB] Absolute maximum Phase shift of ADC clock.");
|
||||
|
||||
INTEGER_COMMAND(vhighvoltage, getHighVoltage, setHighVoltage, std::stoi,
|
||||
"[n_value]\n\tHigh voltage to the sensor in Voltage.\n\t[Gotthard] [0|90|110|120|150|180|200]\n\t[Eiger] 0-200\n\t[Jungfrau][Ctb] [0|60-200]");
|
||||
"[n_value]\n\tHigh voltage to the sensor in Voltage."
|
||||
"\n\t[Gotthard] [0|90|110|120|150|180|200]"
|
||||
"\n\t[Eiger][Mythen3][Gotthard2] 0-200"
|
||||
"\n\t[Jungfrau][Ctb] [0|60-200]");
|
||||
|
||||
INTEGER_COMMAND(powerchip, getPowerChip, setPowerChip, std::stoi,
|
||||
"[0, 1]\n\t[Jungfrau][Mythen3] Power the chip. Default 0.
|
||||
\n\t[Jungfrau] Get will return power status.
|
||||
Can be off if temperature event occured (temperature over temp_threshold with temp_control enabled.
|
||||
\n\t[Mythen3] If module not connected or wrong module, 1 will fail. By default, not powered on");
|
||||
"[0, 1]\n\t[Jungfrau][Mythen3][Gotthard2] Power the chip. Default 0."
|
||||
"\n\t[Jungfrau] Get will return power status."
|
||||
"Can be off if temperature event occured (temperature over temp_threshold with temp_control enabled."
|
||||
"\n\t[Mythen3] If module not connected or wrong module, 1 will fail. By default, not powered on"
|
||||
"\n\t[Gotthard2] If module not connected or wrong module, 1 will fail. By default, powered on at server start up.");
|
||||
|
||||
/** temperature */
|
||||
|
||||
@ -1385,8 +1392,7 @@ class CmdProxy {
|
||||
INTEGER_COMMAND(rx_tcpport, getRxPort, setRxPort, std::stoi,
|
||||
"[port]\n\tTCP port for client-receiver communication. Default is 1954. Must be different if multiple receivers on same pc. Must be first command to set a receiver parameter. Multi command will automatically increment for individual modules.");
|
||||
|
||||
INTEGER_COMMAND(
|
||||
rx_fifodepth, getRxFifoDepth, setRxFifoDepth, std::stoi,
|
||||
INTEGER_COMMAND(rx_fifodepth, getRxFifoDepth, setRxFifoDepth, std::stoi,
|
||||
"[n_frames]\n\tSet the number of frames in the receiver fifo (buffer between listener and writer threads).");
|
||||
|
||||
INTEGER_COMMAND(rx_silent, getRxSilentMode, setRxSilentMode, std::stoi,
|
||||
@ -1686,10 +1692,10 @@ class CmdProxy {
|
||||
"\n\t[Jungfrau][Ctb] Reboot controler (blackfin) of detector.");
|
||||
|
||||
EXECUTE_SET_COMMAND(firmwaretest, executeFirmwareTest,
|
||||
"\n\t[Jungfrau][Ctb][Gotthard] Firmware test, ie. reads a read fixed pattern from a register.");
|
||||
"\n\t[Jungfrau][Gotthard][Mythen3][Gotthard2][Ctb] Firmware test, ie. reads a read fixed pattern from a register.");
|
||||
|
||||
EXECUTE_SET_COMMAND(bustest, executeBusTest,
|
||||
"\n\t[Jungfrau][Ctb][Gotthard] Bus test, ie. keeps writing and reading back different values in R/W register.");
|
||||
"\n\t[Jungfrau][Gotthard][Mythen3][Gotthard2][Ctb] Bus test, ie. keeps writing and reading back different values in R/W register.");
|
||||
|
||||
|
||||
/* Insignificant */
|
||||
@ -1707,13 +1713,13 @@ class CmdProxy {
|
||||
"\n\tClient IP Address that last communicated with the detector.");
|
||||
|
||||
GET_COMMAND(nframes, getNumberOfFramesFromStart,
|
||||
"\n\t[Jungfrau][CTB] Number of frames from start run control.");
|
||||
"\n\t[Jungfrau][Mythen3][Gotthard2][Moench][CTB] Number of frames from start run control.");
|
||||
|
||||
TIME_GET_COMMAND(now, getActualTime,
|
||||
"[(optional unit) ns|us|ms|s]\n\t[Jungfrau][CTB] Time from detector start up.");
|
||||
"[(optional unit) ns|us|ms|s]\n\t[Jungfrau][Mythen3][Gotthard2][Moench][CTB] Time from detector start up.");
|
||||
|
||||
TIME_GET_COMMAND(timestamp, getMeasurementTime,
|
||||
"[(optional unit) ns|us|ms|s]\n\t[Jungfrau][CTB] Timestamp at a frame start.");
|
||||
"[(optional unit) ns|us|ms|s]\n\t[Jungfrau][Mythen3][Gotthard2][Moench][CTB] Timestamp at a frame start.");
|
||||
|
||||
GET_COMMAND(rx_frameindex, getRxCurrentFrameIndex,
|
||||
"\n\tCurrent frame index received in receiver.");
|
||||
|
||||
@ -564,10 +564,10 @@ class slsDetector : public virtual slsDetectorDefs {
|
||||
|
||||
void setPeriod(int64_t value);
|
||||
|
||||
/** [Gotthard][Jungfrau][CTB][Mythen3] */
|
||||
/** [Gotthard][Jungfrau][CTB][Mythen3][Gotthard2] */
|
||||
int64_t getDelayAfterTrigger();
|
||||
|
||||
/** [Gotthard][Jungfrau][CTB][Mythen3] */
|
||||
/** [Gotthard][Jungfrau][CTB][Mythen3][Gotthard2] */
|
||||
void setDelayAfterTrigger(int64_t value);
|
||||
|
||||
/** [Eiger] in 32 bit mode */
|
||||
@ -595,13 +595,13 @@ class slsDetector : public virtual slsDetectorDefs {
|
||||
/** [Gotthard][Jungfrau][CTB][Mythen3][Gotthard2] */
|
||||
int64_t getNumberOfTriggersLeft() const;
|
||||
|
||||
/** [Gotthard][Jungfrau][CTB] */
|
||||
/** [Gotthard][Jungfrau][CTB][Gotthard2] */
|
||||
int64_t getDelayAfterTriggerLeft() const;
|
||||
|
||||
/** [Gotthard] */
|
||||
int64_t getExptimeLeft() const;
|
||||
|
||||
/** [Gotthard][Jungfrau][CTB] */
|
||||
/** [Gotthard][Jungfrau][CTB][Mythen3][Gotthard2] */
|
||||
int64_t getPeriodLeft() const;
|
||||
|
||||
/** [Eiger] minimum two frames */
|
||||
@ -610,13 +610,13 @@ class slsDetector : public virtual slsDetectorDefs {
|
||||
/** [Eiger] */
|
||||
int64_t getMeasuredSubFramePeriod() const;
|
||||
|
||||
/** [Jungfrau][CTB] */
|
||||
/** [Jungfrau][CTB][Mythen3][Gotthard2] */
|
||||
int64_t getNumberOfFramesFromStart() const;
|
||||
|
||||
/** [Jungfrau][CTB] Get time from detector start */
|
||||
/** [Jungfrau][CTB][Mythen3][Gotthard2] Get time from detector start */
|
||||
int64_t getActualTime() const;
|
||||
|
||||
/** [Jungfrau][CTB] Get timestamp at a frame start */
|
||||
/** [Jungfrau][CTB][Mythen3][Gotthard2] Get timestamp at a frame start */
|
||||
int64_t getMeasurementTime() const;
|
||||
|
||||
/**
|
||||
@ -1836,25 +1836,25 @@ class slsDetector : public virtual slsDetectorDefs {
|
||||
*/
|
||||
void setDigitalIODelay(uint64_t pinMask, int delay);
|
||||
|
||||
/** [Gotthard2] */
|
||||
/** [Mythen3][Gotthard2] */
|
||||
int getClockFrequency(int clkIndex);
|
||||
|
||||
/** [Gotthard2] */
|
||||
/** [Mythen3][Gotthard2] */
|
||||
void setClockFrequency(int clkIndex, int value);
|
||||
|
||||
/** [Gotthard2] */
|
||||
/** [Mythen3][Gotthard2] */
|
||||
int getClockPhase(int clkIndex, bool inDegrees);
|
||||
|
||||
/** [Gotthard2] */
|
||||
/** [Mythen3][Gotthard2] */
|
||||
void setClockPhase(int clkIndex, int value, bool inDegrees);
|
||||
|
||||
/** [Gotthard2] */
|
||||
/** [Mythen3][Gotthard2] */
|
||||
int getMaxClockPhaseShift(int clkIndex);
|
||||
|
||||
/** [Gotthard2] */
|
||||
/** [Mythen3][Gotthard2] */
|
||||
int getClockDivider(int clkIndex);
|
||||
|
||||
/** [Gotthard2] */
|
||||
/** [Mythen3][Gotthard2] */
|
||||
void setClockDivider(int clkIndex, int value);
|
||||
|
||||
/** [Ctb][Moench] */
|
||||
|
||||
@ -4,9 +4,9 @@
|
||||
#define APIRECEIVER 0x190722
|
||||
#define APIGUI 0x190723
|
||||
#define APIMOENCH 0x190820
|
||||
#define APIGOTTHARD2 0x191127
|
||||
#define APIGOTTHARD 0x191127
|
||||
#define APIJUNGFRAU 0x191127
|
||||
#define APICTB 0x191210
|
||||
#define APIEIGER 0x200110
|
||||
#define APIMYTHEN3 0x200114
|
||||
#define APIMYTHEN3 0x200115
|
||||
#define APIGOTTHARD2 0x200116
|
||||
|
||||
Reference in New Issue
Block a user