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gotthard2: updated register map; powerchip checking detector type; internal and external period, frames, exptime; set/get delay, get actualtime, measurement, framesfromstart enabled; which detector comment updated in cmdproxy, detector and slsdetector

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This commit is contained in:
maliakal_d
2020-01-16 15:33:35 +01:00
parent b6d9015ed0
commit e8bdf5a505
17 changed files with 661 additions and 261 deletions
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28
slsDetectorServers/mythen3DetectorServer/RegisterDefs.h
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@@ -4,29 +4,38 @@
#define REG_OFFSET (4)
/* Base addresses 0x1804 0000 ---------------------------------------------*/
/* Reconfiguration core for readout pll */
#define BASE_READOUT_PLL (0x0000) // 0x1804_0000 - 0x1804_07FF
/* Reconfiguration core for system pll */
#define BASE_SYSTEM_PLL (0x0800) // 0x1804_0800 - 0x1804_0FFF
/* Clock Generation */
#define BASE_CLK_GENERATION (0x1000) // 0x1804_1000 - 0x1804_XXXX //TODO
/* Base addresses 0x1806 0000 ---------------------------------------------*/
/* General purpose control and status registers */
#define BASE_CONTROL (0x0000) // 0x1806_0000 - 0x1806_00FF https://git.psi.ch/sls_detectors_firmware/mythen_III_mcb/blob/master/code/hdl/ctrl/ctrl.vhd
#define BASE_CONTROL (0x0000) // 0x1806_0000 - 0x1806_00FF
// https://git.psi.ch/sls_detectors_firmware/mythen_III_mcb/blob/master/code/hdl/ctrl/ctrl.vhd
/* ASIC Control */
#define BASE_ASIC (0x0100) // 0x1806_0100 - 0x1806_010F
/* ASIC Digital Interface. Data recovery core */
#define BASE_ADIF (0x0110) // 0x1806_0110 - 0x1806_011F https://git.psi.ch/sls_detectors_firmware/vhdl_library/blob/2e81ccbdbc5cb81813ba190fbdba43e8d6884eb9/adif/adif_ctrl.vhd
#define BASE_ADIF (0x0110) // 0x1806_0110 - 0x1806_011F
// https://git.psi.ch/sls_detectors_firmware/vhdl_library/blob/2e81ccbdbc5cb81813ba190fbdba43e8d6884eb9/adif/adif_ctrl.vhd
/* Formatting of data core */
#define BASE_FMT (0x0120) // 0x1806_0120 - 0x1806_012F
/* Pattern control and status registers */
#define BASE_PATTERN_CONTROL (0x00200) // 0x1806_0200 - 0x1806_02FF https://git.psi.ch/sls_detectors_firmware/vhdl_library/blob/2e81ccbdbc5cb81813ba190fbdba43e8d6884eb9/pattern_flow/pattern_flow_ctrl.vhd
#define BASE_PATTERN_CONTROL (0x00200) // 0x1806_0200 - 0x1806_02FF
// https://git.psi.ch/sls_detectors_firmware/vhdl_library/blob/2e81ccbdbc5cb81813ba190fbdba43e8d6884eb9/pattern_flow/pattern_flow_ctrl.vhd
/* UDP datagram generator */
#define BASE_UDP_RAM (0x01000) // 0x1806_1000 - 0x1806_1FFF
/* Pattern RAM. Pattern table */
#define BASE_PATTERN_RAM (0x10000) // 0x1807_0000 - 0x1807_FFFF
@@ -126,15 +135,15 @@
#define PAT_STATUS_REG (0x00 * REG_OFFSET + BASE_PATTERN_CONTROL)
#define PAT_STATUS_RUN_BUSY_OFST (0)
#define PAT_STATUS_RUN_BUSY_MSK (0x00000001 << PAT_STATUS_RUN_BUSY_OFST)
#define PAT_STATUS_WAIT_FOR_TRGGR_OFST (0)
#define PAT_STATUS_WAIT_FOR_TRGGR_OFST (3)
#define PAT_STATUS_WAIT_FOR_TRGGR_MSK (0x00000001 << PAT_STATUS_WAIT_FOR_TRGGR_OFST)
#define PAT_STATUS_DLY_BFRE_TRGGR_OFST (0)
#define PAT_STATUS_DLY_BFRE_TRGGR_OFST (4)
#define PAT_STATUS_DLY_BFRE_TRGGR_MSK (0x00000001 << PAT_STATUS_DLY_BFRE_TRGGR_OFST)
#define PAT_STATUS_FIFO_FULL_OFST (0)
#define PAT_STATUS_FIFO_FULL_OFST (5)
#define PAT_STATUS_FIFO_FULL_MSK (0x00000001 << PAT_STATUS_FIFO_FULL_OFST)
#define PAT_STATUS_DLY_AFTR_TRGGR_OFST (0)
#define PAT_STATUS_DLY_AFTR_TRGGR_OFST (15)
#define PAT_STATUS_DLY_AFTR_TRGGR_MSK (0x00000001 << PAT_STATUS_DLY_AFTR_TRGGR_OFST)
#define PAT_STATUS_CSM_BUSY_OFST (0)
#define PAT_STATUS_CSM_BUSY_OFST (17)
#define PAT_STATUS_CSM_BUSY_MSK (0x00000001 << PAT_STATUS_CSM_BUSY_OFST)
/* Delay left 64bit Register */
@@ -184,6 +193,9 @@
/* External Signal register */
#define EXT_SIGNAL_REG (0x30 * REG_OFFSET + BASE_PATTERN_CONTROL)
#define EXT_SIGNAL_OFST (0)
#define EXT_SIGNAL_MSK (0x00000001 << EXT_SIGNAL_OFST)
/* Trigger Delay 64 bit register */
#define SET_TRIGGER_DELAY_LSB_REG (0x32 * REG_OFFSET + BASE_PATTERN_CONTROL)
#define SET_TRIGGER_DELAY_MSB_REG (0x33 * REG_OFFSET + BASE_PATTERN_CONTROL)

BIN
slsDetectorServers/mythen3DetectorServer/bin/mythen3DetectorServer_developer
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Binary file not shown.

43
slsDetectorServers/mythen3DetectorServer/slsDetectorFunctionList.c
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@@ -84,13 +84,10 @@ void basictests() {
uint64_t macadd = getDetectorMAC();
int64_t fwversion = getFirmwareVersion();
int64_t swversion = getServerVersion();
int64_t sw_fw_apiversion = 0;
int64_t sw_fw_apiversion = getFirmwareAPIVersion();;
int64_t client_sw_apiversion = getClientServerAPIVersion();
uint32_t requiredFirmwareVersion = REQRD_FRMWRE_VRSN;
if (fwversion >= MIN_REQRD_VRSN_T_RD_API)
sw_fw_apiversion = getFirmwareAPIVersion();
FILE_LOG(logINFOBLUE, ("*************************************************\n"
"Hardware Version:\t\t 0x%x\n"
@@ -609,7 +606,6 @@ int setDelayAfterTrigger(int64_t val) {
int64_t getDelayAfterTrigger() {
return get64BitReg(SET_TRIGGER_DELAY_LSB_REG, SET_TRIGGER_DELAY_MSB_REG) / (1E-9 * FIXED_PLL_FREQUENCY);
}
int64_t getNumFramesLeft() {
@@ -706,10 +702,26 @@ int setHighVoltage(int val){
/* parameters - timing */
void setTiming( enum timingMode arg){
// to be implemented
if(arg != GET_TIMING_MODE){
switch((int)arg){
case AUTO_TIMING:
FILE_LOG(logINFO, ("Set Timing: Auto\n"));
bus_w(EXT_SIGNAL_REG, bus_r(EXT_SIGNAL_REG) & ~EXT_SIGNAL_MSK);
break;
case TRIGGER_EXPOSURE:
FILE_LOG(logINFO, ("Set Timing: Trigger\n"));
bus_w(EXT_SIGNAL_REG, bus_r(EXT_SIGNAL_REG) | EXT_SIGNAL_MSK);
break;
default:
FILE_LOG(logERROR, ("Unknown timing mode %d\n", arg));
return;
}
}
}
enum timingMode getTiming() {
if (bus_r(EXT_SIGNAL_REG) == EXT_SIGNAL_MSK)
return TRIGGER_EXPOSURE;
return AUTO_TIMING;
}
@@ -1068,12 +1080,12 @@ int checkDetectorType() {
}
int type = atoi(buffer);
if (type > TYPE_TOLERANCE) {
FILE_LOG(logERROR, ("No Module attached! Expected %d for Mythen, got %d\n", TYPE_MYTHEN3_MODULE_VAL, type));
FILE_LOG(logERROR, ("No Module attached! Expected %d for Mythen3, got %d\n", TYPE_MYTHEN3_MODULE_VAL, type));
return -2;
}
if (abs(type - TYPE_MYTHEN3_MODULE_VAL) > TYPE_TOLERANCE) {
FILE_LOG(logERROR, ("Wrong Module attached! Expected %d for Mythen, got %d\n", TYPE_MYTHEN3_MODULE_VAL, type));
FILE_LOG(logERROR, ("Wrong Module attached! Expected %d for Mythen3, got %d\n", TYPE_MYTHEN3_MODULE_VAL, type));
return FAIL;
}
return OK;
@@ -1373,7 +1385,7 @@ int stopStateMachine(){
#endif
//stop state machine
bus_w(CONTROL_REG, bus_r(CONTROL_REG) | CONTROL_STP_ACQSTN_MSK);
FILE_LOG(logINFO, ("Status Register: %08x\n",bus_r(STATUS_REG)));
FILE_LOG(logINFO, ("Status Register: %08x\n", bus_r(STATUS_REG)));
return OK;
}
@@ -1430,7 +1442,7 @@ enum runStatus getRunStatus(){
return s;
}
void readFrame(int *ret, char *mess){
void readFrame(int *ret, char *mess) {
// wait for status to be done
while(runBusy()){
usleep(500);
@@ -1450,7 +1462,6 @@ void readFrame(int *ret, char *mess){
} else {
FILE_LOG(logINFOGREEN, ("Acquisition successfully finished\n"));
}
}
u_int32_t runBusy() {
@@ -1464,11 +1475,11 @@ u_int32_t runBusy() {
/* common */
int calculateDataBytes(){
int calculateDataBytes() {
return 0;
}
int getTotalNumberOfChannels(){return ((int)getNumberOfChannelsPerChip() * (int)getNumberOfChips());}
int getNumberOfChips(){return NCHIP;}
int getNumberOfDACs(){return NDAC;}
int getNumberOfChannelsPerChip(){return NCHAN;}
int getTotalNumberOfChannels() {return ((int)getNumberOfChannelsPerChip() * (int)getNumberOfChips());}
int getNumberOfChips() {return NCHIP;}
int getNumberOfDACs() {return NDAC;}
int getNumberOfChannelsPerChip() {return NCHAN;}

4
slsDetectorServers/mythen3DetectorServer/slsDetectorServer_defs.h
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@@ -2,13 +2,12 @@
#include "sls_detector_defs.h"
#define REQRD_FRMWRE_VRSN 0x190000
#define MIN_REQRD_VRSN_T_RD_API 0x190000
#define CTRL_SRVR_INIT_TIME_US (300 * 1000)
/* Hardware Definitions */
#define NCOUNTERS (3)
#define MAX_COUNTER_MSK (0x7)
#define MAX_COUNTER_MSK (0x7)
#define NCHAN (128 * NCOUNTERS)
#define NCHIP (10)
#define NDAC (16)
@@ -45,7 +44,6 @@
#define READOUT_PLL_VCO_FREQ_HZ (1250000000) // 1.25GHz
#define SYSTEM_PLL_VCO_FREQ_HZ (1250000000) // 1.25GHz
#define MAX_PATTERN_LENGTH (0x2000) // maximum number of words (64bit)
#define WAIT_TIME_US_STP_ACQ (100)
/** Other Definitions */
#define BIT16_MASK (0xFFFF)