ctb: added command 'rx_dbitreorder' that sets a flag in the receiver to set the reorder flag. By default it is 1. Setting to false means 'do not reorder' and to keep what the board spits out, which is that all signals in a sample are grouped together

This commit is contained in:
maliakal_d 2025-03-12 17:13:30 +01:00
parent 8d87a6ee4e
commit e8ac048114
20 changed files with 244 additions and 10 deletions

View File

@ -3463,6 +3463,16 @@ class Detector(CppDetectorApi):
def rx_dbitoffset(self, value): def rx_dbitoffset(self, value):
ut.set_using_dict(self.setRxDbitOffset, value) ut.set_using_dict(self.setRxDbitOffset, value)
@property
@element
def rx_dbitreorder(self):
"""[Ctb] Reorder digital data to group together all samples per signal. Default is 1. Setting to 0 means 'do not reorder' and to keep what the board spits out, which is that all signals in a sample are grouped together."""
return self.getRxDbitReorder()
@rx_dbitreorder.setter
def rx_dbitreorder(self, value):
ut.set_using_dict(self.setRxDbitReorder, value)
@property @property
@element @element
def maxadcphaseshift(self): def maxadcphaseshift(self):

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@ -80,7 +80,7 @@ _sd() {
local IS_PATH=0 local IS_PATH=0
local SLS_COMMANDS=" acquire activate adcclk adcenable adcenable10g adcindex adcinvert adclist adcname adcphase adcpipeline adcreg adcvpp apulse asamples autocompdisable badchannels blockingtrigger burstmode burstperiod bursts burstsl bustest cdsgain chipversion clearbit clearbusy clientversion clkdiv clkfreq clkphase collectionmode column compdisabletime confadc config configtransceiver counters currentsource dac dacindex daclist dacname dacvalues datastream dbitclk dbitphase dbitpipeline defaultdac defaultpattern delay delayl detectorserverversion detsize diodelay dpulse dr drlist dsamples execcommand exptime exptime1 exptime2 exptime3 extrastoragecells extsampling extsamplingsrc extsig fformat filtercells filterresistor findex firmwaretest firmwareversion fliprows flowcontrol10g fmaster fname foverwrite fpath framecounter frames framesl frametime free fwrite gaincaps gainmode gappixels gatedelay gatedelay1 gatedelay2 gatedelay3 gates getbit hardwareversion highvoltage hostname im_a im_b im_c im_d im_io imagetest initialchecks inj_ch interpolation interruptsubframe kernelversion lastclient led lock master maxadcphaseshift maxclkphaseshift maxdbitphaseshift measuredperiod measuredsubperiod moduleid nextframenumber nmod numinterfaces overflow packageversion parallel parameters partialreset patfname patioctrl patlimits patloop patloop0 patloop1 patloop2 patmask patnloop patnloop0 patnloop1 patnloop2 patsetbit pattern patternstart patwait patwait0 patwait1 patwait2 patwaittime patwaittime0 patwaittime1 patwaittime2 patword pedestalmode period periodl polarity port powerchip powerindex powerlist powername powervalues programfpga pulse pulsechip pulsenmove pumpprobe quad ratecorr readnrows readout readoutspeed readoutspeedlist rebootcontroller reg resetdacs resetfpga romode row runclk runtime rx_arping rx_clearroi rx_dbitlist rx_dbitoffset rx_discardpolicy rx_fifodepth rx_frameindex rx_framescaught rx_framesperfile rx_hostname rx_jsonaddheader rx_jsonpara rx_lastclient rx_lock rx_missingpackets rx_padding rx_printconfig rx_realudpsocksize rx_roi rx_silent rx_start rx_status rx_stop rx_tcpport rx_threads rx_udpsocksize rx_version rx_zmqfreq rx_zmqhwm rx_zmqip rx_zmqport rx_zmqstartfnum rx_zmqstream samples savepattern scan scanerrmsg selinterface serialnumber setbit settings settingslist settingspath signalindex signallist signalname sleep slowadc slowadcindex slowadclist slowadcname slowadcvalues start status stop stopport storagecell_delay storagecell_start subdeadtime subexptime sync syncclk temp_10ge temp_adc temp_control temp_dcdc temp_event temp_fpga temp_fpgaext temp_fpgafl temp_fpgafr temp_slowadc temp_sodl temp_sodr temp_threshold templist tempvalues tengiga threshold thresholdnotb timing timing_info_decoder timinglist timingsource top transceiverenable trigger triggers triggersl trimbits trimen trimval tsamples txdelay txdelay_frame txdelay_left txdelay_right type udp_cleardst udp_dstip udp_dstip2 udp_dstlist udp_dstmac udp_dstmac2 udp_dstport udp_dstport2 udp_firstdst udp_numdst udp_reconfigure udp_srcip udp_srcip2 udp_srcmac udp_srcmac2 udp_validate update updatedetectorserver updatekernel updatemode user v_a v_b v_c v_chip v_d v_io v_limit vchip_comp_adc vchip_comp_fe vchip_cs vchip_opa_1st vchip_opa_fd vchip_ref_comp_fe versions veto vetoalg vetofile vetophoton vetoref vetostream virtual vm_a vm_b vm_c vm_d vm_io zmqhwm zmqip zmqport " local SLS_COMMANDS=" acquire activate adcclk adcenable adcenable10g adcindex adcinvert adclist adcname adcphase adcpipeline adcreg adcvpp apulse asamples autocompdisable badchannels blockingtrigger burstmode burstperiod bursts burstsl bustest cdsgain chipversion clearbit clearbusy clientversion clkdiv clkfreq clkphase collectionmode column compdisabletime confadc config configtransceiver counters currentsource dac dacindex daclist dacname dacvalues datastream dbitclk dbitphase dbitpipeline defaultdac defaultpattern delay delayl detectorserverversion detsize diodelay dpulse dr drlist dsamples execcommand exptime exptime1 exptime2 exptime3 extrastoragecells extsampling extsamplingsrc extsig fformat filtercells filterresistor findex firmwaretest firmwareversion fliprows flowcontrol10g fmaster fname foverwrite fpath framecounter frames framesl frametime free fwrite gaincaps gainmode gappixels gatedelay gatedelay1 gatedelay2 gatedelay3 gates getbit hardwareversion highvoltage hostname im_a im_b im_c im_d im_io imagetest initialchecks inj_ch interpolation interruptsubframe kernelversion lastclient led lock master maxadcphaseshift maxclkphaseshift maxdbitphaseshift measuredperiod measuredsubperiod moduleid nextframenumber nmod numinterfaces overflow packageversion parallel parameters partialreset patfname patioctrl patlimits patloop patloop0 patloop1 patloop2 patmask patnloop patnloop0 patnloop1 patnloop2 patsetbit pattern patternstart patwait patwait0 patwait1 patwait2 patwaittime patwaittime0 patwaittime1 patwaittime2 patword pedestalmode period periodl polarity port powerchip powerindex powerlist powername powervalues programfpga pulse pulsechip pulsenmove pumpprobe quad ratecorr readnrows readout readoutspeed readoutspeedlist rebootcontroller reg resetdacs resetfpga romode row runclk runtime rx_arping rx_clearroi rx_dbitlist rx_dbitoffset rx_dbitreorder rx_discardpolicy rx_fifodepth rx_frameindex rx_framescaught rx_framesperfile rx_hostname rx_jsonaddheader rx_jsonpara rx_lastclient rx_lock rx_missingpackets rx_padding rx_printconfig rx_realudpsocksize rx_roi rx_silent rx_start rx_status rx_stop rx_tcpport rx_threads rx_udpsocksize rx_version rx_zmqfreq rx_zmqhwm rx_zmqip rx_zmqport rx_zmqstartfnum rx_zmqstream samples savepattern scan scanerrmsg selinterface serialnumber setbit settings settingslist settingspath signalindex signallist signalname sleep slowadc slowadcindex slowadclist slowadcname slowadcvalues start status stop stopport storagecell_delay storagecell_start subdeadtime subexptime sync syncclk temp_10ge temp_adc temp_control temp_dcdc temp_event temp_fpga temp_fpgaext temp_fpgafl temp_fpgafr temp_slowadc temp_sodl temp_sodr temp_threshold templist tempvalues tengiga threshold thresholdnotb timing timing_info_decoder timinglist timingsource top transceiverenable trigger triggers triggersl trimbits trimen trimval tsamples txdelay txdelay_frame txdelay_left txdelay_right type udp_cleardst udp_dstip udp_dstip2 udp_dstlist udp_dstmac udp_dstmac2 udp_dstport udp_dstport2 udp_firstdst udp_numdst udp_reconfigure udp_srcip udp_srcip2 udp_srcmac udp_srcmac2 udp_validate update updatedetectorserver updatekernel updatemode user v_a v_b v_c v_chip v_d v_io v_limit vchip_comp_adc vchip_comp_fe vchip_cs vchip_opa_1st vchip_opa_fd vchip_ref_comp_fe versions veto vetoalg vetofile vetophoton vetoref vetostream virtual vm_a vm_b vm_c vm_d vm_io zmqhwm zmqip zmqport "
__acquire() { __acquire() {
FCN_RETURN="" FCN_RETURN=""
return 0 return 0
@ -2088,6 +2088,15 @@ fi
fi fi
return 0 return 0
} }
__rx_dbitreorder() {
FCN_RETURN=""
if [[ ${IS_GET} -eq 0 ]]; then
if [[ "${cword}" == "2" ]]; then
FCN_RETURN="0 1"
fi
fi
return 0
}
__rx_discardpolicy() { __rx_discardpolicy() {
FCN_RETURN="" FCN_RETURN=""
if [[ ${IS_GET} -eq 0 ]]; then if [[ ${IS_GET} -eq 0 ]]; then

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@ -4,7 +4,7 @@
_sd() { _sd() {
local SLS_COMMANDS=" acquire activate adcclk adcenable adcenable10g adcindex adcinvert adclist adcname adcphase adcpipeline adcreg adcvpp apulse asamples autocompdisable badchannels blockingtrigger burstmode burstperiod bursts burstsl bustest cdsgain chipversion clearbit clearbusy clientversion clkdiv clkfreq clkphase collectionmode column compdisabletime confadc config configtransceiver counters currentsource dac dacindex daclist dacname dacvalues datastream dbitclk dbitphase dbitpipeline defaultdac defaultpattern delay delayl detectorserverversion detsize diodelay dpulse dr drlist dsamples execcommand exptime exptime1 exptime2 exptime3 extrastoragecells extsampling extsamplingsrc extsig fformat filtercells filterresistor findex firmwaretest firmwareversion fliprows flowcontrol10g fmaster fname foverwrite fpath framecounter frames framesl frametime free fwrite gaincaps gainmode gappixels gatedelay gatedelay1 gatedelay2 gatedelay3 gates getbit hardwareversion highvoltage hostname im_a im_b im_c im_d im_io imagetest initialchecks inj_ch interpolation interruptsubframe kernelversion lastclient led lock master maxadcphaseshift maxclkphaseshift maxdbitphaseshift measuredperiod measuredsubperiod moduleid nextframenumber nmod numinterfaces overflow packageversion parallel parameters partialreset patfname patioctrl patlimits patloop patloop0 patloop1 patloop2 patmask patnloop patnloop0 patnloop1 patnloop2 patsetbit pattern patternstart patwait patwait0 patwait1 patwait2 patwaittime patwaittime0 patwaittime1 patwaittime2 patword pedestalmode period periodl polarity port powerchip powerindex powerlist powername powervalues programfpga pulse pulsechip pulsenmove pumpprobe quad ratecorr readnrows readout readoutspeed readoutspeedlist rebootcontroller reg resetdacs resetfpga romode row runclk runtime rx_arping rx_clearroi rx_dbitlist rx_dbitoffset rx_discardpolicy rx_fifodepth rx_frameindex rx_framescaught rx_framesperfile rx_hostname rx_jsonaddheader rx_jsonpara rx_lastclient rx_lock rx_missingpackets rx_padding rx_printconfig rx_realudpsocksize rx_roi rx_silent rx_start rx_status rx_stop rx_tcpport rx_threads rx_udpsocksize rx_version rx_zmqfreq rx_zmqhwm rx_zmqip rx_zmqport rx_zmqstartfnum rx_zmqstream samples savepattern scan scanerrmsg selinterface serialnumber setbit settings settingslist settingspath signalindex signallist signalname sleep slowadc slowadcindex slowadclist slowadcname slowadcvalues start status stop stopport storagecell_delay storagecell_start subdeadtime subexptime sync syncclk temp_10ge temp_adc temp_control temp_dcdc temp_event temp_fpga temp_fpgaext temp_fpgafl temp_fpgafr temp_slowadc temp_sodl temp_sodr temp_threshold templist tempvalues tengiga threshold thresholdnotb timing timing_info_decoder timinglist timingsource top transceiverenable trigger triggers triggersl trimbits trimen trimval tsamples txdelay txdelay_frame txdelay_left txdelay_right type udp_cleardst udp_dstip udp_dstip2 udp_dstlist udp_dstmac udp_dstmac2 udp_dstport udp_dstport2 udp_firstdst udp_numdst udp_reconfigure udp_srcip udp_srcip2 udp_srcmac udp_srcmac2 udp_validate update updatedetectorserver updatekernel updatemode user v_a v_b v_c v_chip v_d v_io v_limit vchip_comp_adc vchip_comp_fe vchip_cs vchip_opa_1st vchip_opa_fd vchip_ref_comp_fe versions veto vetoalg vetofile vetophoton vetoref vetostream virtual vm_a vm_b vm_c vm_d vm_io zmqhwm zmqip zmqport " local SLS_COMMANDS=" acquire activate adcclk adcenable adcenable10g adcindex adcinvert adclist adcname adcphase adcpipeline adcreg adcvpp apulse asamples autocompdisable badchannels blockingtrigger burstmode burstperiod bursts burstsl bustest cdsgain chipversion clearbit clearbusy clientversion clkdiv clkfreq clkphase collectionmode column compdisabletime confadc config configtransceiver counters currentsource dac dacindex daclist dacname dacvalues datastream dbitclk dbitphase dbitpipeline defaultdac defaultpattern delay delayl detectorserverversion detsize diodelay dpulse dr drlist dsamples execcommand exptime exptime1 exptime2 exptime3 extrastoragecells extsampling extsamplingsrc extsig fformat filtercells filterresistor findex firmwaretest firmwareversion fliprows flowcontrol10g fmaster fname foverwrite fpath framecounter frames framesl frametime free fwrite gaincaps gainmode gappixels gatedelay gatedelay1 gatedelay2 gatedelay3 gates getbit hardwareversion highvoltage hostname im_a im_b im_c im_d im_io imagetest initialchecks inj_ch interpolation interruptsubframe kernelversion lastclient led lock master maxadcphaseshift maxclkphaseshift maxdbitphaseshift measuredperiod measuredsubperiod moduleid nextframenumber nmod numinterfaces overflow packageversion parallel parameters partialreset patfname patioctrl patlimits patloop patloop0 patloop1 patloop2 patmask patnloop patnloop0 patnloop1 patnloop2 patsetbit pattern patternstart patwait patwait0 patwait1 patwait2 patwaittime patwaittime0 patwaittime1 patwaittime2 patword pedestalmode period periodl polarity port powerchip powerindex powerlist powername powervalues programfpga pulse pulsechip pulsenmove pumpprobe quad ratecorr readnrows readout readoutspeed readoutspeedlist rebootcontroller reg resetdacs resetfpga romode row runclk runtime rx_arping rx_clearroi rx_dbitlist rx_dbitoffset rx_dbitreorder rx_discardpolicy rx_fifodepth rx_frameindex rx_framescaught rx_framesperfile rx_hostname rx_jsonaddheader rx_jsonpara rx_lastclient rx_lock rx_missingpackets rx_padding rx_printconfig rx_realudpsocksize rx_roi rx_silent rx_start rx_status rx_stop rx_tcpport rx_threads rx_udpsocksize rx_version rx_zmqfreq rx_zmqhwm rx_zmqip rx_zmqport rx_zmqstartfnum rx_zmqstream samples savepattern scan scanerrmsg selinterface serialnumber setbit settings settingslist settingspath signalindex signallist signalname sleep slowadc slowadcindex slowadclist slowadcname slowadcvalues start status stop stopport storagecell_delay storagecell_start subdeadtime subexptime sync syncclk temp_10ge temp_adc temp_control temp_dcdc temp_event temp_fpga temp_fpgaext temp_fpgafl temp_fpgafr temp_slowadc temp_sodl temp_sodr temp_threshold templist tempvalues tengiga threshold thresholdnotb timing timing_info_decoder timinglist timingsource top transceiverenable trigger triggers triggersl trimbits trimen trimval tsamples txdelay txdelay_frame txdelay_left txdelay_right type udp_cleardst udp_dstip udp_dstip2 udp_dstlist udp_dstmac udp_dstmac2 udp_dstport udp_dstport2 udp_firstdst udp_numdst udp_reconfigure udp_srcip udp_srcip2 udp_srcmac udp_srcmac2 udp_validate update updatedetectorserver updatekernel updatemode user v_a v_b v_c v_chip v_d v_io v_limit vchip_comp_adc vchip_comp_fe vchip_cs vchip_opa_1st vchip_opa_fd vchip_ref_comp_fe versions veto vetoalg vetofile vetophoton vetoref vetostream virtual vm_a vm_b vm_c vm_d vm_io zmqhwm zmqip zmqport "
__acquire() { __acquire() {
FCN_RETURN="" FCN_RETURN=""
return 0 return 0
@ -2012,6 +2012,15 @@ fi
fi fi
return 0 return 0
} }
__rx_dbitreorder() {
FCN_RETURN=""
if [[ ${IS_GET} -eq 0 ]]; then
if [[ "${cword}" == "2" ]]; then
FCN_RETURN="0 1"
fi
fi
return 0
}
__rx_discardpolicy() { __rx_discardpolicy() {
FCN_RETURN="" FCN_RETURN=""
if [[ ${IS_GET} -eq 0 ]]; then if [[ ${IS_GET} -eq 0 ]]; then

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@ -1412,6 +1412,18 @@ lock:
function: setDetectorLock function: setDetectorLock
input_types: [ bool ] input_types: [ bool ]
rx_dbitreorder:
help: "[0, 1]\n\t[Ctb] Reorder digital data to group together all samples per signal. Default is 1. Setting to 0 means 'do not reorder' and to keep what the board spits out, which is that all signals in a sample are grouped together."
inherit_actions: INTEGER_COMMAND_VEC_ID
actions:
GET:
function: getRxDbitReorder
PUT:
function: setRxDbitReorder
input_types: [ bool ]
################# INTEGER_COMMAND_VEC_ID_GET ################# ################# INTEGER_COMMAND_VEC_ID_GET #################
master: master:

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@ -8305,6 +8305,47 @@ rx_dbitoffset:
help: "[n_bytes]\n\t[Ctb] Offset in bytes in digital data to skip in receiver." help: "[n_bytes]\n\t[Ctb] Offset in bytes in digital data to skip in receiver."
infer_action: true infer_action: true
template: true template: true
rx_dbitreorder:
actions:
GET:
args:
- arg_types: []
argc: 0
cast_input: []
check_det_id: false
convert_det_id: true
function: getRxDbitReorder
input: []
input_types: []
output:
- OutString(t)
require_det_id: true
store_result_in_t: true
PUT:
args:
- arg_types:
- bool
argc: 1
cast_input:
- true
check_det_id: false
convert_det_id: true
function: setRxDbitReorder
input:
- args[0]
input_types:
- bool
output:
- args.front()
require_det_id: true
store_result_in_t: false
command_name: rx_dbitreorder
function_alias: rx_dbitreorder
help: "[0, 1]\n\t[Ctb] Reorder digital data to group together all samples per signal.\
\ Default is 1. Setting to 0 means 'do not reorder' and to keep what the board\
\ spits out, which is that all signals in a sample are grouped together."
infer_action: true
template: true
rx_discardpolicy: rx_discardpolicy:
actions: actions:
GET: GET:

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@ -1729,6 +1729,15 @@ class Detector {
/** [CTB] Set number of bytes of digital data to skip in the Receiver */ /** [CTB] Set number of bytes of digital data to skip in the Receiver */
void setRxDbitOffset(int value, Positions pos = {}); void setRxDbitOffset(int value, Positions pos = {});
/** [CTB] */
Result<bool> getRxDbitReorder(Positions pos = {}) const;
/** [CTB] Reorder digital data to group together all samples per signal.
* Default is true. Setting to false means 'do not reorder' and to keep what
* the board spits out, which is that all signals in a sample are grouped
* together */
void setRxDbitReorder(bool reorder, Positions pos = {});
/** /**
* [CTB] Set Digital IO Delay * [CTB] Set Digital IO Delay
* cannot get * cannot get

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@ -10700,6 +10700,68 @@ std::string Caller::rx_dbitoffset(int action) {
return os.str(); return os.str();
} }
std::string Caller::rx_dbitreorder(int action) {
std::ostringstream os;
// print help
if (action == slsDetectorDefs::HELP_ACTION) {
os << R"V0G0N([0, 1]
[Ctb] Reorder digital data to group together all samples per signal. Default is 1. Setting to 0 means 'do not reorder' and to keep what the board spits out, which is that all signals in a sample are grouped together. )V0G0N"
<< std::endl;
return os.str();
}
// check if action and arguments are valid
if (action == slsDetectorDefs::GET_ACTION) {
if (1 && args.size() != 0) {
throw RuntimeError("Wrong number of arguments for action GET");
}
if (args.size() == 0) {
}
}
else if (action == slsDetectorDefs::PUT_ACTION) {
if (1 && args.size() != 1) {
throw RuntimeError("Wrong number of arguments for action PUT");
}
if (args.size() == 1) {
try {
StringTo<bool>(args[0]);
} catch (...) {
throw RuntimeError("Could not convert argument 0 to bool");
}
}
}
else {
throw RuntimeError("INTERNAL ERROR: Invalid action: supported actions "
"are ['GET', 'PUT']");
}
// generate code for each action
if (action == slsDetectorDefs::GET_ACTION) {
if (args.size() == 0) {
auto t = det->getRxDbitReorder(std::vector<int>{det_id});
os << OutString(t) << '\n';
}
}
if (action == slsDetectorDefs::PUT_ACTION) {
if (args.size() == 1) {
auto arg0 = StringTo<bool>(args[0]);
det->setRxDbitReorder(arg0, std::vector<int>{det_id});
os << args.front() << '\n';
}
}
return os.str();
}
std::string Caller::rx_discardpolicy(int action) { std::string Caller::rx_discardpolicy(int action) {
std::ostringstream os; std::ostringstream os;

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@ -236,6 +236,7 @@ class Caller {
std::string rx_clearroi(int action); std::string rx_clearroi(int action);
std::string rx_dbitlist(int action); std::string rx_dbitlist(int action);
std::string rx_dbitoffset(int action); std::string rx_dbitoffset(int action);
std::string rx_dbitreorder(int action);
std::string rx_discardpolicy(int action); std::string rx_discardpolicy(int action);
std::string rx_fifodepth(int action); std::string rx_fifodepth(int action);
std::string rx_frameindex(int action); std::string rx_frameindex(int action);
@ -582,6 +583,7 @@ class Caller {
{"rx_clearroi", &Caller::rx_clearroi}, {"rx_clearroi", &Caller::rx_clearroi},
{"rx_dbitlist", &Caller::rx_dbitlist}, {"rx_dbitlist", &Caller::rx_dbitlist},
{"rx_dbitoffset", &Caller::rx_dbitoffset}, {"rx_dbitoffset", &Caller::rx_dbitoffset},
{"rx_dbitreorder", &Caller::rx_dbitreorder},
{"rx_discardpolicy", &Caller::rx_discardpolicy}, {"rx_discardpolicy", &Caller::rx_discardpolicy},
{"rx_fifodepth", &Caller::rx_fifodepth}, {"rx_fifodepth", &Caller::rx_fifodepth},
{"rx_frameindex", &Caller::rx_frameindex}, {"rx_frameindex", &Caller::rx_frameindex},

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@ -2277,6 +2277,14 @@ void Detector::setRxDbitOffset(int value, Positions pos) {
pimpl->Parallel(&Module::setReceiverDbitOffset, pos, value); pimpl->Parallel(&Module::setReceiverDbitOffset, pos, value);
} }
Result<bool> Detector::getRxDbitReorder(Positions pos) const {
return pimpl->Parallel(&Module::getReceiverDbitReorder, pos);
}
void Detector::setRxDbitReorder(bool reorder, Positions pos) {
pimpl->Parallel(&Module::setReceiverDbitReorder, pos, reorder);
}
void Detector::setDigitalIODelay(uint64_t pinMask, int delay, Positions pos) { void Detector::setDigitalIODelay(uint64_t pinMask, int delay, Positions pos) {
pimpl->Parallel(&Module::setDigitalIODelay, pos, pinMask, delay); pimpl->Parallel(&Module::setDigitalIODelay, pos, pinMask, delay);
} }

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@ -2509,6 +2509,15 @@ void Module::setReceiverDbitOffset(int value) {
sendToReceiver(F_SET_RECEIVER_DBIT_OFFSET, value, nullptr); sendToReceiver(F_SET_RECEIVER_DBIT_OFFSET, value, nullptr);
} }
bool Module::getReceiverDbitReorder() const {
return sendToReceiver<int>(F_GET_RECEIVER_DBIT_REORDER);
}
void Module::setReceiverDbitReorder(bool reorder) {
sendToReceiver(F_SET_RECEIVER_DBIT_REORDER, static_cast<int>(reorder),
nullptr);
}
void Module::setDigitalIODelay(uint64_t pinMask, int delay) { void Module::setDigitalIODelay(uint64_t pinMask, int delay) {
uint64_t args[]{pinMask, static_cast<uint64_t>(delay)}; uint64_t args[]{pinMask, static_cast<uint64_t>(delay)};
sendToDetector(F_DIGITAL_IO_DELAY, args, nullptr); sendToDetector(F_DIGITAL_IO_DELAY, args, nullptr);

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@ -510,6 +510,8 @@ class Module : public virtual slsDetectorDefs {
void setReceiverDbitList(std::vector<int> list); void setReceiverDbitList(std::vector<int> list);
int getReceiverDbitOffset() const; int getReceiverDbitOffset() const;
void setReceiverDbitOffset(int value); void setReceiverDbitOffset(int value);
bool getReceiverDbitReorder() const;
void setReceiverDbitReorder(bool value);
void setDigitalIODelay(uint64_t pinMask, int delay); void setDigitalIODelay(uint64_t pinMask, int delay);
bool getLEDEnable() const; bool getLEDEnable() const;
void setLEDEnable(bool enable); void setLEDEnable(bool enable);

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@ -2568,6 +2568,22 @@ int InferAction::rx_dbitoffset() {
} }
} }
int InferAction::rx_dbitreorder() {
if (args.size() == 0) {
return slsDetectorDefs::GET_ACTION;
}
if (args.size() == 1) {
return slsDetectorDefs::PUT_ACTION;
}
else {
throw RuntimeError("Could not infer action: Wrong number of arguments");
}
}
int InferAction::rx_discardpolicy() { int InferAction::rx_discardpolicy() {
if (args.size() == 0) { if (args.size() == 0) {

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@ -193,6 +193,7 @@ class InferAction {
int rx_clearroi(); int rx_clearroi();
int rx_dbitlist(); int rx_dbitlist();
int rx_dbitoffset(); int rx_dbitoffset();
int rx_dbitreorder();
int rx_discardpolicy(); int rx_discardpolicy();
int rx_fifodepth(); int rx_fifodepth();
int rx_frameindex(); int rx_frameindex();
@ -527,6 +528,7 @@ class InferAction {
{"rx_clearroi", &InferAction::rx_clearroi}, {"rx_clearroi", &InferAction::rx_clearroi},
{"rx_dbitlist", &InferAction::rx_dbitlist}, {"rx_dbitlist", &InferAction::rx_dbitlist},
{"rx_dbitoffset", &InferAction::rx_dbitoffset}, {"rx_dbitoffset", &InferAction::rx_dbitoffset},
{"rx_dbitreorder", &InferAction::rx_dbitreorder},
{"rx_discardpolicy", &InferAction::rx_discardpolicy}, {"rx_discardpolicy", &InferAction::rx_discardpolicy},
{"rx_fifodepth", &InferAction::rx_fifodepth}, {"rx_fifodepth", &InferAction::rx_fifodepth},
{"rx_frameindex", &InferAction::rx_frameindex}, {"rx_frameindex", &InferAction::rx_frameindex},

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@ -218,6 +218,8 @@ int ClientInterface::functionTable(){
flist[F_RECEIVER_SET_TRANSCEIVER_MASK] = &ClientInterface::set_transceiver_mask; flist[F_RECEIVER_SET_TRANSCEIVER_MASK] = &ClientInterface::set_transceiver_mask;
flist[F_RECEIVER_SET_ROW] = &ClientInterface::set_row; flist[F_RECEIVER_SET_ROW] = &ClientInterface::set_row;
flist[F_RECEIVER_SET_COLUMN] = &ClientInterface::set_column; flist[F_RECEIVER_SET_COLUMN] = &ClientInterface::set_column;
flist[F_GET_RECEIVER_DBIT_REORDER] = &ClientInterface::get_dbit_reorder;
flist[F_SET_RECEIVER_DBIT_REORDER] = &ClientInterface::set_dbit_reorder;
for (int i = NUM_DET_FUNCTIONS + 1; i < NUM_REC_FUNCTIONS ; i++) { for (int i = NUM_DET_FUNCTIONS + 1; i < NUM_REC_FUNCTIONS ; i++) {
@ -1789,4 +1791,25 @@ int ClientInterface::set_column(Interface &socket) {
return socket.Send(OK); return socket.Send(OK);
} }
int ClientInterface::get_dbit_reorder(Interface &socket) {
if (detType != CHIPTESTBOARD && detType != XILINX_CHIPTESTBOARD)
functionNotImplemented();
int retval = impl()->getDbitReorder();
LOG(logDEBUG1) << "Dbit reorder retval: " << retval;
return socket.sendResult(retval);
}
int ClientInterface::set_dbit_reorder(Interface &socket) {
auto arg = socket.Receive<int>();
if (detType != CHIPTESTBOARD && detType != XILINX_CHIPTESTBOARD)
functionNotImplemented();
if (arg < 0) {
throw RuntimeError("Invalid dbit reorder: " + std::to_string(arg));
}
verifyIdle(socket);
LOG(logDEBUG1) << "Setting Dbit offset: " << arg;
impl()->setDbitReorder(arg);
return socket.Send(OK);
}
} // namespace sls } // namespace sls

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@ -164,6 +164,8 @@ class ClientInterface : private virtual slsDetectorDefs {
int set_transceiver_mask(ServerInterface &socket); int set_transceiver_mask(ServerInterface &socket);
int set_row(ServerInterface &socket); int set_row(ServerInterface &socket);
int set_column(ServerInterface &socket); int set_column(ServerInterface &socket);
int get_dbit_reorder(ServerInterface &socket);
int set_dbit_reorder(ServerInterface &socket);
Implementation *impl() { Implementation *impl() {
if (receiver != nullptr) { if (receiver != nullptr) {

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@ -75,10 +75,10 @@ void DataProcessor::SetCtbDbitList(std::vector<int> value) {
ctbDbitList = value; ctbDbitList = value;
} }
void DataProcessor::SetReorder(const bool value) { reorder = value; }
void DataProcessor::SetCtbDbitOffset(int value) { ctbDbitOffset = value; } void DataProcessor::SetCtbDbitOffset(int value) { ctbDbitOffset = value; }
void DataProcessor::SetCtbDbitReorder(bool value) { ctbDbitReorder = value; }
void DataProcessor::SetQuadEnable(bool value) { quadEnable = value; } void DataProcessor::SetQuadEnable(bool value) { quadEnable = value; }
void DataProcessor::SetFlipRows(bool fd) { void DataProcessor::SetFlipRows(bool fd) {
@ -556,7 +556,7 @@ void DataProcessor::ArrangeDbitData(size_t &size, char *data) {
0; // number of bytes for selected digital data given by dtbDbitList 0; // number of bytes for selected digital data given by dtbDbitList
// store each selected bit from all samples consecutively // store each selected bit from all samples consecutively
if (reorder) { if (ctbDbitReorder) {
int numBitsPerDbit = numDigitalSamples; // num bits per selected digital int numBitsPerDbit = numDigitalSamples; // num bits per selected digital
// Bit for all samples // Bit for all samples
if ((numBitsPerDbit % 8) != 0) if ((numBitsPerDbit % 8) != 0)
@ -575,7 +575,7 @@ void DataProcessor::ArrangeDbitData(size_t &size, char *data) {
std::vector<uint8_t> result(totalNumBytes, 0); std::vector<uint8_t> result(totalNumBytes, 0);
uint8_t *dest = &result[0]; uint8_t *dest = &result[0];
if (reorder) { if (ctbDbitReorder) {
// loop through digital bit enable vector // loop through digital bit enable vector
int bitoffset = 0; int bitoffset = 0;
for (auto bi : ctbDbitList) { for (auto bi : ctbDbitList) {

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@ -46,8 +46,8 @@ class DataProcessor : private virtual slsDetectorDefs, public ThreadObject {
void SetStreamingStartFnum(uint32_t value); void SetStreamingStartFnum(uint32_t value);
void SetFramePadding(bool enable); void SetFramePadding(bool enable);
void SetCtbDbitList(std::vector<int> value); void SetCtbDbitList(std::vector<int> value);
void SetReorder(const bool reorder);
void SetCtbDbitOffset(int value); void SetCtbDbitOffset(int value);
void SetCtbDbitReorder(bool value);
void SetQuadEnable(bool value); void SetQuadEnable(bool value);
void SetFlipRows(bool fd); void SetFlipRows(bool fd);
void SetNumberofTotalFrames(uint64_t value); void SetNumberofTotalFrames(uint64_t value);
@ -168,8 +168,8 @@ class DataProcessor : private virtual slsDetectorDefs, public ThreadObject {
struct timespec timerbegin {}; struct timespec timerbegin {};
bool framePadding; bool framePadding;
std::vector<int> ctbDbitList; std::vector<int> ctbDbitList;
bool reorder{false}; // true if data should be reordered TODO: add as mode int ctbDbitOffset{0};
int ctbDbitOffset; bool ctbDbitReorder{false};
std::atomic<bool> startedFlag{false}; std::atomic<bool> startedFlag{false};
std::atomic<uint64_t> firstIndex{0}; std::atomic<uint64_t> firstIndex{0};
bool quadEnable{false}; bool quadEnable{false};

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@ -202,6 +202,7 @@ void Implementation::SetupDataProcessor(int i) {
dataProcessor[i]->SetFramePadding(framePadding); dataProcessor[i]->SetFramePadding(framePadding);
dataProcessor[i]->SetCtbDbitList(ctbDbitList); dataProcessor[i]->SetCtbDbitList(ctbDbitList);
dataProcessor[i]->SetCtbDbitOffset(ctbDbitOffset); dataProcessor[i]->SetCtbDbitOffset(ctbDbitOffset);
dataProcessor[i]->SetCtbDbitReorder(ctbDbitReorder);
dataProcessor[i]->SetQuadEnable(quadEnable); dataProcessor[i]->SetQuadEnable(quadEnable);
dataProcessor[i]->SetFlipRows(flipRows); dataProcessor[i]->SetFlipRows(flipRows);
dataProcessor[i]->SetNumberofTotalFrames(numberOfTotalFrames); dataProcessor[i]->SetNumberofTotalFrames(numberOfTotalFrames);
@ -1766,6 +1767,15 @@ void Implementation::setDbitOffset(const int s) {
LOG(logINFO) << "Dbit offset: " << ctbDbitOffset; LOG(logINFO) << "Dbit offset: " << ctbDbitOffset;
} }
bool Implementation::getDbitReorder() const { return ctbDbitReorder; }
void Implementation::setDbitReorder(const bool reorder) {
ctbDbitReorder = reorder;
for (const auto &it : dataProcessor)
it->SetCtbDbitReorder(ctbDbitReorder);
LOG(logINFO) << "Dbit reorder: " << ctbDbitReorder;
}
uint32_t Implementation::getTransceiverEnableMask() const { uint32_t Implementation::getTransceiverEnableMask() const {
return generalData->transceiverMask; return generalData->transceiverMask;
} }

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@ -252,6 +252,10 @@ class Implementation : private virtual slsDetectorDefs {
int getDbitOffset() const; int getDbitOffset() const;
/* [Ctb] */ /* [Ctb] */
void setDbitOffset(const int s); void setDbitOffset(const int s);
bool getDbitReorder() const;
/* [Ctb] */
void setDbitReorder(const bool reorder);
uint32_t getTransceiverEnableMask() const; uint32_t getTransceiverEnableMask() const;
/* [Ctb] */ /* [Ctb] */
void setTransceiverEnableMask(const uint32_t mask); void setTransceiverEnableMask(const uint32_t mask);
@ -368,6 +372,7 @@ class Implementation : private virtual slsDetectorDefs {
std::vector<int64_t> rateCorrections; std::vector<int64_t> rateCorrections;
std::vector<int> ctbDbitList; std::vector<int> ctbDbitList;
int ctbDbitOffset{0}; int ctbDbitOffset{0};
bool ctbDbitReorder{true};
// callbacks // callbacks
void (*startAcquisitionCallBack)(const startCallbackHeader, void (*startAcquisitionCallBack)(const startCallbackHeader,

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@ -410,6 +410,8 @@ enum detFuncs {
F_RECEIVER_SET_TRANSCEIVER_MASK, F_RECEIVER_SET_TRANSCEIVER_MASK,
F_RECEIVER_SET_ROW, F_RECEIVER_SET_ROW,
F_RECEIVER_SET_COLUMN, F_RECEIVER_SET_COLUMN,
F_GET_RECEIVER_DBIT_REORDER,
F_SET_RECEIVER_DBIT_REORDER,
NUM_REC_FUNCTIONS NUM_REC_FUNCTIONS
}; };
@ -816,7 +818,8 @@ const char* getFunctionNameFromEnum(enum detFuncs func) {
case F_RECEIVER_SET_TRANSCEIVER_MASK: return "F_RECEIVER_SET_TRANSCEIVER_MASK"; case F_RECEIVER_SET_TRANSCEIVER_MASK: return "F_RECEIVER_SET_TRANSCEIVER_MASK";
case F_RECEIVER_SET_ROW: return "F_RECEIVER_SET_ROW"; case F_RECEIVER_SET_ROW: return "F_RECEIVER_SET_ROW";
case F_RECEIVER_SET_COLUMN: return "F_RECEIVER_SET_COLUMN"; case F_RECEIVER_SET_COLUMN: return "F_RECEIVER_SET_COLUMN";
case F_GET_RECEIVER_DBIT_REORDER: return "F_GET_RECEIVER_DBIT_REORDER";
case F_SET_RECEIVER_DBIT_REORDER: return "F_SET_RECEIVER_DBIT_REORDER";
case NUM_REC_FUNCTIONS: return "NUM_REC_FUNCTIONS"; case NUM_REC_FUNCTIONS: return "NUM_REC_FUNCTIONS";
default: return "Unknown Function"; default: return "Unknown Function";