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Pattern unification & Matterhorn Changes (#1303)
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* update ctb regDefs, included fill level of adc, transceiver and DBit fifos, added enable registers for cont. readout

* fix fifo fill level range bug

* updated ctb RegDefs, increased size of fifo fill level register

* added register to read the firmware git hash

* ctb: added altchip_id read register

* start with unification of pattern machinery for xctb, ctb, mythen

* udate addrs for d-server internal matterhorn startup

* update xctb reg defs

* move pattern loopdef start

* added zero trimbits to matterhorn config

* Revert "added zero trimbits to matterhorn config"

This reverts commit 7c347badd5.

* added adjustable clocks on Xilinx-CTB

* added support for fractional dividers of runclk

* XCTB: make frequencies adjustable from python gui

* update docs

* added support for patternstart command to XCTB

* XCTB: map pattern_ram directly into memory, removed rw strobe

* refactor Mythen pattern control addresses

* test altera ctb with common addresses, removed ifdefs

* change ordering of regdefs

* updated python help for dbitclk, adcclk and runclk (khz)

* xilinx: moved the wait for firmware to measure the actual frequency to the server side and removed it in the pyctbgui side

* will not be anymore in developer branch

* make format (exception RegisterDefs.h), rewrite XILINX PLL to have less consstants in the code

* bug: mixing && for &

---------

Co-authored-by: Martin Mueller <martin.mueller@psi.ch>
Co-authored-by: Dhanya Thattil <dhanya.thattil@psi.ch>
This commit is contained in:
Martin Mueller
2025-09-17 17:28:17 +02:00
committed by GitHub
parent 6e006665ef
commit e7a91d38f2
33 changed files with 795 additions and 951 deletions
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11
slsDetectorSoftware/src/Caller.cpp
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@@ -73,7 +73,8 @@ std::string Caller::adcclk(int action) {
// print help
if (action == slsDetectorDefs::HELP_ACTION) {
os << R"V0G0N([n_clk in MHz]
[Ctb] ADC clock frequency in MHz. )V0G0N"
[Ctb] ADC clock frequency in MHz.
[xilinx Ctb] ADC clock frequency in kHz. )V0G0N"
<< std::endl;
return os.str();
}
@@ -2805,7 +2806,8 @@ std::string Caller::dbitclk(int action) {
// print help
if (action == slsDetectorDefs::HELP_ACTION) {
os << R"V0G0N([n_clk in MHz]
[Ctb] Clock for latching the digital bits in MHz. )V0G0N"
[Ctb] Clock for latching the digital bits in MHz.
[xilinx Ctb] Clock for latching the digital bits in kHz. )V0G0N"
<< std::endl;
return os.str();
}
@@ -8452,7 +8454,7 @@ std::string Caller::patternstart(int action) {
// print help
if (action == slsDetectorDefs::HELP_ACTION) {
os << R"V0G0N(
[Mythen3] Starts Pattern )V0G0N"
[Mythen3][Xilinx Ctb] Starts Pattern )V0G0N"
<< std::endl;
return os.str();
}
@@ -10429,7 +10431,8 @@ std::string Caller::runclk(int action) {
// print help
if (action == slsDetectorDefs::HELP_ACTION) {
os << R"V0G0N([n_clk in MHz]
[Ctb] Run clock in MHz. )V0G0N"
[Ctb] Run clock in MHz.
[xilinx Ctb] Run clock in kHz. )V0G0N"
<< std::endl;
return os.str();
}