Pattern unification & Matterhorn Changes (#1303)

* update ctb regDefs, included fill level of adc, transceiver and DBit fifos, added enable registers for cont. readout

* fix fifo fill level range bug

* updated ctb RegDefs, increased size of fifo fill level register

* added register to read the firmware git hash

* ctb: added altchip_id read register

* start with unification of pattern machinery for xctb, ctb, mythen

* udate addrs for d-server internal matterhorn startup

* update xctb reg defs

* move pattern loopdef start

* added zero trimbits to matterhorn config

* Revert "added zero trimbits to matterhorn config"

This reverts commit 7c347badd5.

* added adjustable clocks on Xilinx-CTB

* added support for fractional dividers of runclk

* XCTB: make frequencies adjustable from python gui

* update docs

* added support for patternstart command to XCTB

* XCTB: map pattern_ram directly into memory, removed rw strobe

* refactor Mythen pattern control addresses

* test altera ctb with common addresses, removed ifdefs

* change ordering of regdefs

* updated python help for dbitclk, adcclk and runclk (khz)

* xilinx: moved the wait for firmware to measure the actual frequency to the server side and removed it in the pyctbgui side

* will not be anymore in developer branch

* make format (exception RegisterDefs.h), rewrite XILINX PLL to have less consstants in the code

* bug: mixing && for &

---------

Co-authored-by: Martin Mueller <martin.mueller@psi.ch>
Co-authored-by: Dhanya Thattil <dhanya.thattil@psi.ch>

slsDetectorSoftware/generator/extended_commands.yaml

@@ -106,7 +106,8 @@ adcclk:
         store_result_in_t: false
   command_name: adcclk
   function_alias: adcclk
-  help: "[n_clk in MHz]\n\t[Ctb] ADC clock frequency in MHz."
+  help: "[n_clk in MHz]\n\t[Ctb] ADC clock frequency in MHz.\n\t[xilinx Ctb] ADC clock\
+    \ frequency in kHz."
   infer_action: true
   template: true
 adcenable:
@@ -2219,7 +2220,8 @@ dbitclk:
         store_result_in_t: false
   command_name: dbitclk
   function_alias: dbitclk
-  help: "[n_clk in MHz]\n\t[Ctb] Clock for latching the digital bits in MHz."
+  help: "[n_clk in MHz]\n\t[Ctb] Clock for latching the digital bits in MHz.\n\t[xilinx\
+    \ Ctb] Clock for latching the digital bits in kHz."
   infer_action: true
   template: true
 dbitphase:
@@ -6515,7 +6517,7 @@ patternstart:
         store_result_in_t: false
   command_name: patternstart
   function_alias: patternstart
-  help: "\n\t[Mythen3] Starts Pattern"
+  help: "\n\t[Mythen3][Xilinx Ctb] Starts Pattern"
   infer_action: true
   template: true
 patwait:
@@ -8133,7 +8135,7 @@ runclk:
         store_result_in_t: false
   command_name: runclk
   function_alias: runclk
-  help: "[n_clk in MHz]\n\t[Ctb] Run clock in MHz."
+  help: "[n_clk in MHz]\n\t[Ctb] Run clock in MHz.\n\t[xilinx Ctb] Run clock in kHz."
   infer_action: true
   template: true
 runtime: