mirror of
https://github.com/slsdetectorgroup/slsDetectorPackage.git
synced 2026-01-16 08:39:21 +01:00
Pattern unification & Matterhorn Changes (#1303)
* update ctb regDefs, included fill level of adc, transceiver and DBit fifos, added enable registers for cont. readout
* fix fifo fill level range bug
* updated ctb RegDefs, increased size of fifo fill level register
* added register to read the firmware git hash
* ctb: added altchip_id read register
* start with unification of pattern machinery for xctb, ctb, mythen
* udate addrs for d-server internal matterhorn startup
* update xctb reg defs
* move pattern loopdef start
* added zero trimbits to matterhorn config
* Revert "added zero trimbits to matterhorn config"
This reverts commit 7c347badd5.
* added adjustable clocks on Xilinx-CTB
* added support for fractional dividers of runclk
* XCTB: make frequencies adjustable from python gui
* update docs
* added support for patternstart command to XCTB
* XCTB: map pattern_ram directly into memory, removed rw strobe
* refactor Mythen pattern control addresses
* test altera ctb with common addresses, removed ifdefs
* change ordering of regdefs
* updated python help for dbitclk, adcclk and runclk (khz)
* xilinx: moved the wait for firmware to measure the actual frequency to the server side and removed it in the pyctbgui side
* will not be anymore in developer branch
* make format (exception RegisterDefs.h), rewrite XILINX PLL to have less consstants in the code
* bug: mixing && for &
---------
Co-authored-by: Martin Mueller <martin.mueller@psi.ch>
Co-authored-by: Dhanya Thattil <dhanya.thattil@psi.ch>
This commit is contained in:
Martin Mueller
@@ -2,10 +2,16 @@
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// Copyright (C) 2021 Contributors to the SLS Detector Package
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#pragma once
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// clang-format off
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#define REG_OFFSET (4)
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#define PATTERN_STEP0_MSB_REG (0x10004)
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#define PATTERN_STEP0_LSB_REG (0x10000)
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#define CTRL_REG (0x8000)
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#define POWER_VIO_OFST (0)
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#define POWER_VIO_MSK (0x00000001 << POWER_VIO_OFST)
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#define POWER_VIO_OFST (0)
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#define POWER_VIO_MSK (0x00000001 << POWER_VIO_OFST)
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#define POWER_VCC_A_OFST (1)
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#define POWER_VCC_A_MSK (0x00000001 << POWER_VCC_A_OFST)
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#define POWER_VCC_B_OFST (2)
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@@ -17,20 +23,20 @@
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#define STATUS_REG (0x8004)
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#define PATTERN_RUNNING_OFST (0)
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#define PATTERN_RUNNING_MSK (0x00000001 << PATTERN_RUNNING_OFST)
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#define RX_BUSY_OFST (1)
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#define RX_BUSY_MSK (0x00000001 << RX_BUSY_OFST)
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#define PROCESSING_BUSY_OFST (2)
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#define PROCESSING_BUSY_MSK (0x00000001 << PROCESSING_BUSY_OFST)
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#define UDP_GEN_BUSY_OFST (3)
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#define UDP_GEN_BUSY_MSK (0x00000001 << UDP_GEN_BUSY_OFST)
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#define NETWORK_BUSY_OFST (4)
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#define NETWORK_BUSY_MSK (0x00000001 << NETWORK_BUSY_OFST)
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#define PATTERN_RUNNING_OFST (0)
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#define PATTERN_RUNNING_MSK (0x00000001 << PATTERN_RUNNING_OFST)
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#define RX_BUSY_OFST (1)
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#define RX_BUSY_MSK (0x00000001 << RX_BUSY_OFST)
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#define PROCESSING_BUSY_OFST (2)
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#define PROCESSING_BUSY_MSK (0x00000001 << PROCESSING_BUSY_OFST)
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#define UDP_GEN_BUSY_OFST (3)
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#define UDP_GEN_BUSY_MSK (0x00000001 << UDP_GEN_BUSY_OFST)
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#define NETWORK_BUSY_OFST (4)
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#define NETWORK_BUSY_MSK (0x00000001 << NETWORK_BUSY_OFST)
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#define WAIT_FOR_TRIGGER_OFST (5)
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#define WAIT_FOR_TRIGGER_MSK (0x00000001 << WAIT_FOR_TRIGGER_OFST)
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#define RX_NOT_GOOD_OFST (6)
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#define RX_NOT_GOOD_MSK (0x00000001 << RX_NOT_GOOD_OFST)
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#define RX_NOT_GOOD_OFST (6)
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#define RX_NOT_GOOD_MSK (0x00000001 << RX_NOT_GOOD_OFST)
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#define STATUS_REG2 (0x8008)
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@@ -38,8 +44,8 @@
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#define FPGACOMPDATE_OFST (0)
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#define FPGACOMPDATE_MSK (0x00ffffff << FPGACOMPDATE_OFST)
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#define FPGADETTYPE_OFST (24)
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#define FPGADETTYPE_MSK (0x000000ff << FPGADETTYPE_OFST)
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#define FPGADETTYPE_OFST (24)
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#define FPGADETTYPE_MSK (0x000000ff << FPGADETTYPE_OFST)
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#define FPGA_GIT_HEAD (0x8010)
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@@ -50,8 +56,8 @@
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#define APICOMPDATE_OFST (0)
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#define APICOMPDATE_MSK (0x00ffffff << APICOMPDATE_OFST)
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#define APIDETTYPE_OFST (24)
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#define APIDETTYPE_MSK (0x000000ff << APIDETTYPE_OFST)
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#define APIDETTYPE_OFST (24)
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#define APIDETTYPE_MSK (0x000000ff << APIDETTYPE_OFST)
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#define A_FIFO_OVERFLOW_STATUS_REG (0x9000)
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@@ -103,23 +109,22 @@
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#define FIFO_TO_GB_CONTROL_REG (0xA000)
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#define ENABLED_CHANNELS_ADC_OFST (0)
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#define ENABLED_CHANNELS_ADC_MSK (0x000000ff << ENABLED_CHANNELS_ADC_OFST)
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#define ENABLED_CHANNELS_D_OFST (8)
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#define ENABLED_CHANNELS_D_MSK (0x00000001 << ENABLED_CHANNELS_D_OFST)
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#define ENABLED_CHANNELS_X_OFST (9)
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#define ENABLED_CHANNELS_X_MSK (0x0000000f << ENABLED_CHANNELS_X_OFST)
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#define RO_MODE_ADC_OFST (13)
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#define RO_MODE_ADC_MSK (0x00000001 << RO_MODE_ADC_OFST)
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#define RO_MODE_D_OFST (14)
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#define RO_MODE_D_MSK (0x00000001 << RO_MODE_D_OFST)
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#define RO_MODE_X_OFST (15)
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#define RO_MODE_X_MSK (0x00000001 << RO_MODE_X_OFST)
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#define ENABLED_CHANNELS_ADC_OFST (0)
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#define ENABLED_CHANNELS_ADC_MSK (0x000000ff << ENABLED_CHANNELS_ADC_OFST)
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#define ENABLED_CHANNELS_D_OFST (8)
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#define ENABLED_CHANNELS_D_MSK (0x00000001 << ENABLED_CHANNELS_D_OFST)
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#define ENABLED_CHANNELS_X_OFST (9)
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#define ENABLED_CHANNELS_X_MSK (0x0000000f << ENABLED_CHANNELS_X_OFST)
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#define RO_MODE_ADC_OFST (13)
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#define RO_MODE_ADC_MSK (0x00000001 << RO_MODE_ADC_OFST)
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#define RO_MODE_D_OFST (14)
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#define RO_MODE_D_MSK (0x00000001 << RO_MODE_D_OFST)
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#define RO_MODE_X_OFST (15)
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#define RO_MODE_X_MSK (0x00000001 << RO_MODE_X_OFST)
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#define COUNT_FRAMES_FROM_UPDATE_OFST (16)
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#define COUNT_FRAMES_FROM_UPDATE_MSK \
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(0x00000001 << COUNT_FRAMES_FROM_UPDATE_OFST)
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#define START_STREAMING_P_OFST (17)
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#define START_STREAMING_P_MSK (0x00000001 << START_STREAMING_P_OFST)
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#define COUNT_FRAMES_FROM_UPDATE_MSK (0x00000001 << COUNT_FRAMES_FROM_UPDATE_OFST)
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#define START_STREAMING_P_OFST (17)
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#define START_STREAMING_P_MSK (0x00000001 << START_STREAMING_P_OFST)
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#define STREAM_BUFFER_CLEAR_OFST (18)
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#define STREAM_BUFFER_CLEAR_MSK (0x00000001 << STREAM_BUFFER_CLEAR_OFST)
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@@ -148,26 +153,26 @@
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#define PKTPACKETLENGTHREG (0xA020)
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#define PACKETLENGTH1G_OFST (0)
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#define PACKETLENGTH1G_MSK (0x0000ffff << PACKETLENGTH1G_OFST)
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#define PACKETLENGTH1G_OFST (0)
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#define PACKETLENGTH1G_MSK (0x0000ffff << PACKETLENGTH1G_OFST)
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#define PACKETLENGTH10G_OFST (16)
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#define PACKETLENGTH10G_MSK (0x0000ffff << PACKETLENGTH10G_OFST)
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#define PKTNOPACKETSREG (0xA024)
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#define NOPACKETS1G_OFST (0)
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#define NOPACKETS1G_MSK (0x0000003f << NOPACKETS1G_OFST)
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#define NOPACKETS1G_OFST (0)
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#define NOPACKETS1G_MSK (0x0000003f << NOPACKETS1G_OFST)
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#define NOPACKETS10G_OFST (16)
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#define NOPACKETS10G_MSK (0x0000003f << NOPACKETS10G_OFST)
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#define PKTCTRLREG (0xA028)
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#define NOSERVERS_OFST (0)
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#define NOSERVERS_MSK (0x0000003f << NOSERVERS_OFST)
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#define NOSERVERS_OFST (0)
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#define NOSERVERS_MSK (0x0000003f << NOSERVERS_OFST)
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#define SERVERSTART_OFST (8)
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#define SERVERSTART_MSK (0x0000001f << SERVERSTART_OFST)
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#define ETHINTERF_OFST (16)
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#define ETHINTERF_MSK (0x00000001 << ETHINTERF_OFST)
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#define ETHINTERF_OFST (16)
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#define ETHINTERF_MSK (0x00000001 << ETHINTERF_OFST)
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#define PKTCOORDREG1 (0xA02C)
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@@ -181,363 +186,282 @@
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#define COORDZ_OFST (0)
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#define COORDZ_MSK (0x0000ffff << COORDZ_OFST)
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#define FLOW_STATUS_REG (0xB000)
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#define PATTERN_OUT_LSB_REG (0xB000)
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#define RSM_BUSY_OFST (0)
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#define RSM_BUSY_MSK (0x00000001 << RSM_BUSY_OFST)
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#define RSM_TRG_WAIT_OFST (3)
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#define RSM_TRG_WAIT_MSK (0x00000001 << RSM_TRG_WAIT_OFST)
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#define CSM_BUSY_OFST (17)
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#define CSM_BUSY_MSK (0x00000001 << CSM_BUSY_OFST)
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#define PATTERN_OUT_MSB_REG (0xB004)
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#define FLOW_CONTROL_REG (0xB004)
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#define PATTERN_IN_LSB_REG (0xB008)
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#define START_F_OFST (0)
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#define START_F_MSK (0x00000001 << START_F_OFST)
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#define STOP_F_OFST (1)
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#define STOP_F_MSK (0x00000001 << STOP_F_OFST)
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#define RST_F_OFST (2)
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#define RST_F_MSK (0x00000001 << RST_F_OFST)
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#define SW_TRIGGER_F_OFST (3)
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#define SW_TRIGGER_F_MSK (0x00000001 << SW_TRIGGER_F_OFST)
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#define TRIGGER_ENABLE_OFST (4)
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#define TRIGGER_ENABLE_MSK (0x00000001 << TRIGGER_ENABLE_OFST)
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#define PATTERN_IN_MSB_REG (0xB00C)
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#define TIME_FROM_START_OUT_REG_1 (0xB008)
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#define PATTERN_MASK_LSB_REG (0xB010)
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#define TIME_FROM_START_OUT_REG_2 (0xB00C)
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#define PATTERN_MASK_MSB_REG (0xB014)
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#define FRAMES_FROM_START_OUT_REG_1 (0xB010)
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#define PATTERN_SET_LSB_REG (0xB018)
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#define FRAMES_FROM_START_OUT_REG_2 (0xB014)
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#define PATTERN_SET_MSB_REG (0xB01C)
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#define FRAME_TIME_OUT_REG_1 (0xB018)
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#define PATTERN_CNTRL_REG (0xB020)
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#define FRAME_TIME_OUT_REG_2 (0xB01C)
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#define DELAY_OUT_REG_1 (0xB020)
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#define DELAY_OUT_REG_2 (0xB024)
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#define CYCLES_OUT_REG_1 (0xB028)
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#define CYCLES_OUT_REG_2 (0xB02C)
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#define FRAMES_OUT_REG_1 (0xB030)
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#define FRAMES_OUT_REG_2 (0xB034)
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#define PERIOD_OUT_REG_1 (0xB038)
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#define PERIOD_OUT_REG_2 (0xB03C)
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#define DELAY_IN_REG_1 (0xB040)
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#define DELAY_IN_REG_2 (0xB044)
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#define CYCLES_IN_REG_1 (0xB048)
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#define CYCLES_IN_REG_2 (0xB04C)
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#define FRAMES_IN_REG_1 (0xB050)
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#define FRAMES_IN_REG_2 (0xB054)
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#define PERIOD_IN_REG_1 (0xB058)
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#define PERIOD_IN_REG_2 (0xB05C)
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#define PATTERN_OUT_LSB_REG (0xB100)
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#define PATTERN_OUT_MSB_REG (0xB104)
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#define PATTERN_IN_LSB_REG (0xB108)
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#define PATTERN_IN_MSB_REG (0xB10C)
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#define PATTERN_MASK_LSB_REG (0xB110)
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#define PATTERN_MASK_MSB_REG (0xB114)
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#define PATTERN_SET_LSB_REG (0xB118)
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#define PATTERN_SET_MSB_REG (0xB11C)
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#define PATTERN_CNTRL_REG (0xB120)
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#define PATTERN_CNTRL_WR_OFST (0)
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#define PATTERN_CNTRL_WR_MSK (0x00000001 << PATTERN_CNTRL_WR_OFST)
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#define PATTERN_CNTRL_RD_OFST (1)
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#define PATTERN_CNTRL_RD_MSK (0x00000001 << PATTERN_CNTRL_RD_OFST)
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#define PATTERN_CNTRL_WR_OFST (0)
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#define PATTERN_CNTRL_WR_MSK (0x00000001 << PATTERN_CNTRL_WR_OFST)
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#define PATTERN_CNTRL_RD_OFST (1)
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#define PATTERN_CNTRL_RD_MSK (0x00000001 << PATTERN_CNTRL_RD_OFST)
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#define PATTERN_CNTRL_ADDR_OFST (16)
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#define PATTERN_CNTRL_ADDR_MSK (0x00001fff << PATTERN_CNTRL_ADDR_OFST)
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#define PATTERN_LIMIT_REG (0xB124)
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#define PATTERN_LIMIT_REG (0xB024)
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#define PATTERN_LIMIT_STRT_OFST (0)
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#define PATTERN_LIMIT_STRT_MSK (0x00001fff << PATTERN_LIMIT_STRT_OFST)
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#define PATTERN_LIMIT_STP_OFST (16)
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#define PATTERN_LIMIT_STP_MSK (0x00001fff << PATTERN_LIMIT_STP_OFST)
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#define PATTERN_LIMIT_STP_OFST (16)
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#define PATTERN_LIMIT_STP_MSK (0x00001fff << PATTERN_LIMIT_STP_OFST)
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#define PATTERN_LOOP_0_ADDR_REG (0xB128)
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#define PATTERN_IO_CNTRL_LSB_REG (0xB028)
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#define PATTERN_LOOP_0_ADDR_STRT_OFST (0)
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#define PATTERN_LOOP_0_ADDR_STRT_MSK \
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(0x00001fff << PATTERN_LOOP_0_ADDR_STRT_OFST)
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#define PATTERN_LOOP_0_ADDR_STP_OFST (16)
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#define PATTERN_LOOP_0_ADDR_STP_MSK (0x00001fff << PATTERN_LOOP_0_ADDR_STP_OFST)
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#define PATTERN_IO_CNTRL_MSB_REG (0xB02C)
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#define PATTERN_LOOP_0_ITERATION_REG (0xB12C)
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#define FLOW_CONTROL_REG (0xB030)
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#define PATTERN_WAIT_0_ADDR_REG (0xB130)
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#define START_F_OFST (0)
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#define START_F_MSK (0x00000001 << START_F_OFST)
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#define STOP_F_OFST (1)
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#define STOP_F_MSK (0x00000001 << STOP_F_OFST)
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#define RST_F_OFST (2)
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#define RST_F_MSK (0x00000001 << RST_F_OFST)
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#define SW_TRIGGER_F_OFST (3)
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#define SW_TRIGGER_F_MSK (0x00000001 << SW_TRIGGER_F_OFST)
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#define TRIGGER_ENABLE_OFST (4)
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#define TRIGGER_ENABLE_MSK (0x00000001 << TRIGGER_ENABLE_OFST)
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#define RSM_BUSY_OFST (5)
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#define RSM_BUSY_MSK (0x00000001 << RSM_BUSY_OFST)
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#define RSM_TRG_WAIT_OFST (6)
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#define RSM_TRG_WAIT_MSK (0x00000001 << RSM_TRG_WAIT_OFST)
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#define CSM_BUSY_OFST (7)
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#define CSM_BUSY_MSK (0x00000001 << CSM_BUSY_OFST)
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#define PATTERN_WAIT_0_ADDR_OFST (0)
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#define PATTERN_WAIT_0_ADDR_MSK (0x00001fff << PATTERN_WAIT_0_ADDR_OFST)
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#define DELAY_IN_REG_1 (0xB034)
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#define PATTERN_WAIT_TIMER_0_LSB_REG (0xB134)
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#define DELAY_IN_REG_2 (0xB038)
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#define PATTERN_WAIT_TIMER_0_MSB_REG (0xB138)
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#define CYCLES_IN_REG_1 (0xB03C)
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#define PATTERN_LOOP_1_ADDR_REG (0xB13C)
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#define CYCLES_IN_REG_2 (0xB040)
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#define PATTERN_LOOP_1_ADDR_STRT_OFST (0)
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#define PATTERN_LOOP_1_ADDR_STRT_MSK \
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(0x00001fff << PATTERN_LOOP_1_ADDR_STRT_OFST)
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#define PATTERN_LOOP_1_ADDR_STP_OFST (16)
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#define PATTERN_LOOP_1_ADDR_STP_MSK (0x00001fff << PATTERN_LOOP_1_ADDR_STP_OFST)
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#define FRAMES_IN_REG_1 (0xB044)
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#define PATTERN_LOOP_1_ITERATION_REG (0xB140)
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#define FRAMES_IN_REG_2 (0xB048)
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#define PATTERN_WAIT_1_ADDR_REG (0xB144)
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#define PERIOD_IN_REG_1 (0xB04C)
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#define PATTERN_WAIT_1_ADDR_OFST (0)
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#define PATTERN_WAIT_1_ADDR_MSK (0x00001fff << PATTERN_WAIT_1_ADDR_OFST)
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#define PERIOD_IN_REG_2 (0xB050)
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#define PATTERN_WAIT_TIMER_1_LSB_REG (0xB148)
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#define PATTERN_TEST_REG (0xB054)
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#define PATTERN_WAIT_TIMER_1_MSB_REG (0xB14C)
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#define PATTERN_FIRMWARE_REG (0xB058)
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#define PATTERN_LOOP_2_ADDR_REG (0xB150)
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#define PATTERN_WIDTH_OFST (0)
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#define PATTERN_WIDTH_MSK (0x000000ff << PATTERN_WIDTH_OFST)
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#define PATTERN_ADDR_WIDTH_OFST (8)
|
||||
#define PATTERN_ADDR_WIDTH_MSK (0x000000ff << PATTERN_ADDR_WIDTH_OFST)
|
||||
#define PATTERN_NLOOPS_NWAITS_OFST (16)
|
||||
#define PATTERN_NLOOPS_NWAITS_MSK (0x000000ff << PATTERN_NLOOPS_NWAITS_OFST)
|
||||
#define DIRECT_PATTERN_RAM_OFST (24)
|
||||
#define DIRECT_PATTERN_RAM_MSK (0x00000001 << DIRECT_PATTERN_RAM_OFST)
|
||||
|
||||
#define PATTERN_LOOP_2_ADDR_STRT_OFST (0)
|
||||
#define PATTERN_LOOP_2_ADDR_STRT_MSK \
|
||||
(0x00001fff << PATTERN_LOOP_2_ADDR_STRT_OFST)
|
||||
#define PATTERN_LOOP_2_ADDR_STP_OFST (16)
|
||||
#define PATTERN_LOOP_2_ADDR_STP_MSK (0x00001fff << PATTERN_LOOP_2_ADDR_STP_OFST)
|
||||
#define TIME_FROM_START_OUT_REG_1 (0xB05C)
|
||||
|
||||
#define PATTERN_LOOP_2_ITERATION_REG (0xB154)
|
||||
#define TIME_FROM_START_OUT_REG_2 (0xB060)
|
||||
|
||||
#define PATTERN_WAIT_2_ADDR_REG (0xB158)
|
||||
#define FRAMES_FROM_START_OUT_REG_1 (0xB064)
|
||||
|
||||
#define PATTERN_WAIT_2_ADDR_OFST (0)
|
||||
#define PATTERN_WAIT_2_ADDR_MSK (0x00001fff << PATTERN_WAIT_2_ADDR_OFST)
|
||||
#define FRAMES_FROM_START_OUT_REG_2 (0xB068)
|
||||
|
||||
#define PATTERN_WAIT_TIMER_2_LSB_REG (0xB15C)
|
||||
#define FRAME_TIME_OUT_REG_1 (0xB06C)
|
||||
|
||||
#define PATTERN_WAIT_TIMER_2_MSB_REG (0xB160)
|
||||
#define FRAME_TIME_OUT_REG_2 (0xB070)
|
||||
|
||||
#define PATTERN_LOOP_3_ADDR_REG (0xB164)
|
||||
#define PATTERN_LOOPDEF_BASE (0xB080)
|
||||
|
||||
#define PATTERN_LOOP_3_ADDR_STRT_OFST (0)
|
||||
#define PATTERN_LOOP_3_ADDR_STRT_MSK \
|
||||
(0x00001fff << PATTERN_LOOP_3_ADDR_STRT_OFST)
|
||||
#define PATTERN_LOOP_3_ADDR_STP_OFST (16)
|
||||
#define PATTERN_LOOP_3_ADDR_STP_MSK (0x00001fff << PATTERN_LOOP_3_ADDR_STP_OFST)
|
||||
#define PATTERN_LOOP_ADDR_WORD_OFST (0)
|
||||
#define PATTERN_LOOP_ADDR_WORD_MSK (0x00000001 << PATTERN_LOOP_ADDR_WORD_OFST)
|
||||
#define PATTERN_LOOP_ITERATION_WORD_OFST (1)
|
||||
#define PATTERN_LOOP_ITERATION_WORD_MSK (0x00000001 << PATTERN_LOOP_ITERATION_WORD_OFST)
|
||||
#define PATTERN_WAIT_ADDR_WORD_OFST (2)
|
||||
#define PATTERN_WAIT_ADDR_WORD_MSK (0x00000001 << PATTERN_WAIT_ADDR_WORD_OFST)
|
||||
#define PATTERN_WAIT_TIMER_LSB_WORD_OFST (3)
|
||||
#define PATTERN_WAIT_TIMER_LSB_WORD_MSK (0x00000001 << PATTERN_WAIT_TIMER_LSB_WORD_OFST)
|
||||
#define PATTERN_WAIT_TIMER_MSB_WORD_OFST (4)
|
||||
#define PATTERN_WAIT_TIMER_MSB_WORD_MSK (0x00000001 << PATTERN_WAIT_TIMER_MSB_WORD_OFST)
|
||||
#define PATTERN_LOOPDEF_NWORDS_OFST (5)
|
||||
#define PATTERN_LOOPDEF_NWORDS_MSK (0x00000001 << PATTERN_LOOPDEF_NWORDS_OFST)
|
||||
#define PATTERN_WAIT_ADDR_OFST (0)
|
||||
#define PATTERN_WAIT_ADDR_MSK (0x00001fff << PATTERN_WAIT_ADDR_OFST)
|
||||
#define PATTERN_LOOP_ADDR_STRT_OFST (0)
|
||||
#define PATTERN_LOOP_ADDR_STRT_MSK (0x00001fff << PATTERN_LOOP_ADDR_STRT_OFST)
|
||||
#define PATTERN_LOOP_ADDR_STP_OFST (16)
|
||||
#define PATTERN_LOOP_ADDR_STP_MSK (0x00001fff << PATTERN_LOOP_ADDR_STP_OFST)
|
||||
|
||||
#define PATTERN_LOOP_3_ITERATION_REG (0xB168)
|
||||
#define DBITFIFOCTRLREG (0xC000)
|
||||
|
||||
#define PATTERN_WAIT_3_ADDR_REG (0xB16C)
|
||||
|
||||
#define PATTERN_WAIT_3_ADDR_OFST (0)
|
||||
#define PATTERN_WAIT_3_ADDR_MSK (0x00001fff << PATTERN_WAIT_3_ADDR_OFST)
|
||||
|
||||
#define PATTERN_WAIT_TIMER_3_LSB_REG (0xB170)
|
||||
|
||||
#define PATTERN_WAIT_TIMER_3_MSB_REG (0xB174)
|
||||
|
||||
#define PATTERN_LOOP_4_ADDR_REG (0xB178)
|
||||
|
||||
#define PATTERN_LOOP_4_ADDR_STRT_OFST (0)
|
||||
#define PATTERN_LOOP_4_ADDR_STRT_MSK \
|
||||
(0x00001fff << PATTERN_LOOP_4_ADDR_STRT_OFST)
|
||||
#define PATTERN_LOOP_4_ADDR_STP_OFST (16)
|
||||
#define PATTERN_LOOP_4_ADDR_STP_MSK (0x00001fff << PATTERN_LOOP_4_ADDR_STP_OFST)
|
||||
|
||||
#define PATTERN_LOOP_4_ITERATION_REG (0xB17C)
|
||||
|
||||
#define PATTERN_WAIT_4_ADDR_REG (0xB180)
|
||||
|
||||
#define PATTERN_WAIT_4_ADDR_OFST (0)
|
||||
#define PATTERN_WAIT_4_ADDR_MSK (0x00001fff << PATTERN_WAIT_4_ADDR_OFST)
|
||||
|
||||
#define PATTERN_WAIT_TIMER_4_LSB_REG (0xB184)
|
||||
|
||||
#define PATTERN_WAIT_TIMER_4_MSB_REG (0xB188)
|
||||
|
||||
#define PATTERN_LOOP_5_ADDR_REG (0xB18C)
|
||||
|
||||
#define PATTERN_LOOP_5_ADDR_STRT_OFST (0)
|
||||
#define PATTERN_LOOP_5_ADDR_STRT_MSK \
|
||||
(0x00001fff << PATTERN_LOOP_5_ADDR_STRT_OFST)
|
||||
#define PATTERN_LOOP_5_ADDR_STP_OFST (16)
|
||||
#define PATTERN_LOOP_5_ADDR_STP_MSK (0x00001fff << PATTERN_LOOP_5_ADDR_STP_OFST)
|
||||
|
||||
#define PATTERN_LOOP_5_ITERATION_REG (0xB190)
|
||||
|
||||
#define PATTERN_WAIT_5_ADDR_REG (0xB194)
|
||||
|
||||
#define PATTERN_WAIT_5_ADDR_OFST (0)
|
||||
#define PATTERN_WAIT_5_ADDR_MSK (0x00001fff << PATTERN_WAIT_5_ADDR_OFST)
|
||||
|
||||
#define PATTERN_WAIT_TIMER_5_LSB_REG (0xB198)
|
||||
|
||||
#define PATTERN_WAIT_TIMER_5_MSB_REG (0xB19C)
|
||||
|
||||
#define PINIOCTRLREG (0xB1A0)
|
||||
|
||||
#define DBITFIFOCTRLREG (0xB1A4)
|
||||
|
||||
#define DBITRD_OFST (0)
|
||||
#define DBITRD_MSK (0x00000001 << DBITRD_OFST)
|
||||
#define DBITRST_OFST (1)
|
||||
#define DBITRST_MSK (0x00000001 << DBITRST_OFST)
|
||||
#define DBITFULL_OFST (2)
|
||||
#define DBITFULL_MSK (0x00000001 << DBITFULL_OFST)
|
||||
#define DBITEMPTY_OFST (3)
|
||||
#define DBITEMPTY_MSK (0x00000001 << DBITEMPTY_OFST)
|
||||
#define DBITRD_OFST (0)
|
||||
#define DBITRD_MSK (0x00000001 << DBITRD_OFST)
|
||||
#define DBITRST_OFST (1)
|
||||
#define DBITRST_MSK (0x00000001 << DBITRST_OFST)
|
||||
#define DBITFULL_OFST (2)
|
||||
#define DBITFULL_MSK (0x00000001 << DBITFULL_OFST)
|
||||
#define DBITEMPTY_OFST (3)
|
||||
#define DBITEMPTY_MSK (0x00000001 << DBITEMPTY_OFST)
|
||||
#define DBITUNDERFLOW_OFST (4)
|
||||
#define DBITUNDERFLOW_MSK (0x00000001 << DBITUNDERFLOW_OFST)
|
||||
#define DBITOVERFLOW_OFST (5)
|
||||
#define DBITOVERFLOW_MSK (0x00000001 << DBITOVERFLOW_OFST)
|
||||
#define DBITOVERFLOW_OFST (5)
|
||||
#define DBITOVERFLOW_MSK (0x00000001 << DBITOVERFLOW_OFST)
|
||||
|
||||
#define DBITFIFODATAREG1 (0xB1A8)
|
||||
#define DBITFIFODATAREG1 (0xC004)
|
||||
|
||||
#define DBITFIFODATAREG2 (0xB1AC)
|
||||
#define DBITFIFODATAREG2 (0xC008)
|
||||
|
||||
#define MATTERHORNSPIREG1 (0xB1B0)
|
||||
#define MATTERHORNSPIREG1 (0xC00C)
|
||||
|
||||
#define MATTERHORNSPIREG2 (0xB1B4)
|
||||
#define MATTERHORNSPIREG2 (0xC010)
|
||||
|
||||
#define MATTERHORNSPICTRL (0xB1B8)
|
||||
#define MATTERHORNSPICTRL (0xC014)
|
||||
|
||||
#define CONFIGSTART_P_OFST (0)
|
||||
#define CONFIGSTART_P_MSK (0x00000001 << CONFIGSTART_P_OFST)
|
||||
#define PERIPHERYRST_P_OFST (1)
|
||||
#define PERIPHERYRST_P_MSK (0x00000001 << PERIPHERYRST_P_OFST)
|
||||
#define STARTREAD_P_OFST (2)
|
||||
#define STARTREAD_P_MSK (0x00000001 << STARTREAD_P_OFST)
|
||||
#define BUSY_OFST (3)
|
||||
#define BUSY_MSK (0x00000001 << BUSY_OFST)
|
||||
#define CONFIGSTART_P_OFST (0)
|
||||
#define CONFIGSTART_P_MSK (0x00000001 << CONFIGSTART_P_OFST)
|
||||
#define PERIPHERYRST_P_OFST (1)
|
||||
#define PERIPHERYRST_P_MSK (0x00000001 << PERIPHERYRST_P_OFST)
|
||||
#define STARTREAD_P_OFST (2)
|
||||
#define STARTREAD_P_MSK (0x00000001 << STARTREAD_P_OFST)
|
||||
#define BUSY_OFST (3)
|
||||
#define BUSY_MSK (0x00000001 << BUSY_OFST)
|
||||
#define READOUTFROMASIC_OFST (4)
|
||||
#define READOUTFROMASIC_MSK (0x00000001 << READOUTFROMASIC_OFST)
|
||||
|
||||
#define TRANSCEIVERRXCTRL0REG1 (0xB800)
|
||||
#define TRANSCEIVERRXCTRL0REG1 (0xC100)
|
||||
|
||||
#define TRANSCEIVERRXCTRL0REG2 (0xB804)
|
||||
#define TRANSCEIVERRXCTRL0REG2 (0xC104)
|
||||
|
||||
#define TRANSCEIVERRXCTRL1REG1 (0xB808)
|
||||
#define TRANSCEIVERRXCTRL1REG1 (0xC108)
|
||||
|
||||
#define TRANSCEIVERRXCTRL1REG2 (0xB80C)
|
||||
#define TRANSCEIVERRXCTRL1REG2 (0xC10C)
|
||||
|
||||
#define TRANSCEIVERRXCTRL2REG (0xB810)
|
||||
#define TRANSCEIVERRXCTRL2REG (0xC110)
|
||||
|
||||
#define TRANSCEIVERRXCTRL3REG (0xB814)
|
||||
#define TRANSCEIVERRXCTRL3REG (0xC114)
|
||||
|
||||
#define TRANSCEIVERSTATUS (0xB818)
|
||||
#define TRANSCEIVERSTATUS (0xC118)
|
||||
|
||||
#define LINKDOWNLATCHEDOUT_OFST (0)
|
||||
#define LINKDOWNLATCHEDOUT_MSK (0x00000001 << LINKDOWNLATCHEDOUT_OFST)
|
||||
#define TXUSERCLKACTIVE_OFST (1)
|
||||
#define TXUSERCLKACTIVE_MSK (0x00000001 << TXUSERCLKACTIVE_OFST)
|
||||
#define RXUSERCLKACTIVE_OFST (2)
|
||||
#define RXUSERCLKACTIVE_MSK (0x00000001 << RXUSERCLKACTIVE_OFST)
|
||||
#define RXCOMMADET_OFST (3)
|
||||
#define RXCOMMADET_MSK (0x0000000f << RXCOMMADET_OFST)
|
||||
#define RXBYTEREALIGN_OFST (7)
|
||||
#define RXBYTEREALIGN_MSK (0x0000000f << RXBYTEREALIGN_OFST)
|
||||
#define RXBYTEISALIGNED_OFST (11)
|
||||
#define RXBYTEISALIGNED_MSK (0x0000000f << RXBYTEISALIGNED_OFST)
|
||||
#define GTWIZRXCDRSTABLE_OFST (15)
|
||||
#define GTWIZRXCDRSTABLE_MSK (0x00000001 << GTWIZRXCDRSTABLE_OFST)
|
||||
#define RESETTXDONE_OFST (16)
|
||||
#define RESETTXDONE_MSK (0x00000001 << RESETTXDONE_OFST)
|
||||
#define RESETRXDONE_OFST (17)
|
||||
#define RESETRXDONE_MSK (0x00000001 << RESETRXDONE_OFST)
|
||||
#define RXPMARESETDONE_OFST (18)
|
||||
#define RXPMARESETDONE_MSK (0x0000000f << RXPMARESETDONE_OFST)
|
||||
#define TXPMARESETDONE_OFST (22)
|
||||
#define TXPMARESETDONE_MSK (0x0000000f << TXPMARESETDONE_OFST)
|
||||
#define GTTPOWERGOOD_OFST (26)
|
||||
#define GTTPOWERGOOD_MSK (0x0000000f << GTTPOWERGOOD_OFST)
|
||||
#define TXUSERCLKACTIVE_OFST (1)
|
||||
#define TXUSERCLKACTIVE_MSK (0x00000001 << TXUSERCLKACTIVE_OFST)
|
||||
#define RXUSERCLKACTIVE_OFST (2)
|
||||
#define RXUSERCLKACTIVE_MSK (0x00000001 << RXUSERCLKACTIVE_OFST)
|
||||
#define RXCOMMADET_OFST (3)
|
||||
#define RXCOMMADET_MSK (0x0000000f << RXCOMMADET_OFST)
|
||||
#define RXBYTEREALIGN_OFST (7)
|
||||
#define RXBYTEREALIGN_MSK (0x0000000f << RXBYTEREALIGN_OFST)
|
||||
#define RXBYTEISALIGNED_OFST (11)
|
||||
#define RXBYTEISALIGNED_MSK (0x0000000f << RXBYTEISALIGNED_OFST)
|
||||
#define GTWIZRXCDRSTABLE_OFST (15)
|
||||
#define GTWIZRXCDRSTABLE_MSK (0x00000001 << GTWIZRXCDRSTABLE_OFST)
|
||||
#define RESETTXDONE_OFST (16)
|
||||
#define RESETTXDONE_MSK (0x00000001 << RESETTXDONE_OFST)
|
||||
#define RESETRXDONE_OFST (17)
|
||||
#define RESETRXDONE_MSK (0x00000001 << RESETRXDONE_OFST)
|
||||
#define RXPMARESETDONE_OFST (18)
|
||||
#define RXPMARESETDONE_MSK (0x0000000f << RXPMARESETDONE_OFST)
|
||||
#define TXPMARESETDONE_OFST (22)
|
||||
#define TXPMARESETDONE_MSK (0x0000000f << TXPMARESETDONE_OFST)
|
||||
#define GTTPOWERGOOD_OFST (26)
|
||||
#define GTTPOWERGOOD_MSK (0x0000000f << GTTPOWERGOOD_OFST)
|
||||
|
||||
#define TRANSCEIVERSTATUS2 (0xB81C)
|
||||
#define TRANSCEIVERSTATUS2 (0xC11C)
|
||||
|
||||
#define RXLOCKED_OFST (0)
|
||||
#define RXLOCKED_MSK (0x0000000f << RXLOCKED_OFST)
|
||||
|
||||
#define TRANSCEIVERCONTROL (0xB820)
|
||||
#define TRANSCEIVERCONTROL (0xC120)
|
||||
|
||||
#define GTWIZRESETALL_OFST (0)
|
||||
#define GTWIZRESETALL_MSK (0x00000001 << GTWIZRESETALL_OFST)
|
||||
#define GTWIZRESETALL_OFST (0)
|
||||
#define GTWIZRESETALL_MSK (0x00000001 << GTWIZRESETALL_OFST)
|
||||
#define RESETTXPLLANDDATAPATH_OFST (1)
|
||||
#define RESETTXPLLANDDATAPATH_MSK (0x00000001 << RESETTXPLLANDDATAPATH_OFST)
|
||||
#define RESETTXDATAPATHIN_OFST (2)
|
||||
#define RESETTXDATAPATHIN_MSK (0x00000001 << RESETTXDATAPATHIN_OFST)
|
||||
#define RESETTXDATAPATHIN_OFST (2)
|
||||
#define RESETTXDATAPATHIN_MSK (0x00000001 << RESETTXDATAPATHIN_OFST)
|
||||
#define RESETRXPLLANDDATAPATH_OFST (3)
|
||||
#define RESETRXPLLANDDATAPATH_MSK (0x00000001 << RESETRXPLLANDDATAPATH_OFST)
|
||||
#define RESETRXDATAPATHIN_OFST (4)
|
||||
#define RESETRXDATAPATHIN_MSK (0x00000001 << RESETRXDATAPATHIN_OFST)
|
||||
#define RXPOLARITY_OFST (5)
|
||||
#define RXPOLARITY_MSK (0x0000000f << RXPOLARITY_OFST)
|
||||
#define RXERRORCNTRESET_OFST (9)
|
||||
#define RXERRORCNTRESET_MSK (0x0000000f << RXERRORCNTRESET_OFST)
|
||||
#define RXMSBLSBINVERT_OFST (13)
|
||||
#define RXMSBLSBINVERT_MSK (0x0000000f << RXMSBLSBINVERT_OFST)
|
||||
#define RESETRXDATAPATHIN_OFST (4)
|
||||
#define RESETRXDATAPATHIN_MSK (0x00000001 << RESETRXDATAPATHIN_OFST)
|
||||
#define RXPOLARITY_OFST (5)
|
||||
#define RXPOLARITY_MSK (0x0000000f << RXPOLARITY_OFST)
|
||||
#define RXERRORCNTRESET_OFST (9)
|
||||
#define RXERRORCNTRESET_MSK (0x0000000f << RXERRORCNTRESET_OFST)
|
||||
#define RXMSBLSBINVERT_OFST (13)
|
||||
#define RXMSBLSBINVERT_MSK (0x0000000f << RXMSBLSBINVERT_OFST)
|
||||
|
||||
#define TRANSCEIVERERRCNT_REG0 (0xB824)
|
||||
#define TRANSCEIVERERRCNT_REG0 (0xC124)
|
||||
|
||||
#define TRANSCEIVERERRCNT_REG1 (0xB828)
|
||||
#define TRANSCEIVERERRCNT_REG1 (0xC128)
|
||||
|
||||
#define TRANSCEIVERERRCNT_REG2 (0xB82C)
|
||||
#define TRANSCEIVERERRCNT_REG2 (0xC12C)
|
||||
|
||||
#define TRANSCEIVERERRCNT_REG3 (0xB830)
|
||||
#define TRANSCEIVERERRCNT_REG3 (0xC130)
|
||||
|
||||
#define TRANSCEIVERALIGNCNT_REG0 (0xB834)
|
||||
#define TRANSCEIVERALIGNCNT_REG0 (0xC134)
|
||||
|
||||
#define RXALIGNCNTCH0_OFST (0)
|
||||
#define RXALIGNCNTCH0_MSK (0x0000ffff << RXALIGNCNTCH0_OFST)
|
||||
|
||||
#define TRANSCEIVERALIGNCNT_REG1 (0xB838)
|
||||
#define TRANSCEIVERALIGNCNT_REG1 (0xC138)
|
||||
|
||||
#define RXALIGNCNTCH1_OFST (0)
|
||||
#define RXALIGNCNTCH1_MSK (0x0000ffff << RXALIGNCNTCH1_OFST)
|
||||
|
||||
#define TRANSCEIVERALIGNCNT_REG2 (0xB83C)
|
||||
#define TRANSCEIVERALIGNCNT_REG2 (0xC13C)
|
||||
|
||||
#define RXALIGNCNTCH2_OFST (0)
|
||||
#define RXALIGNCNTCH2_MSK (0x0000ffff << RXALIGNCNTCH2_OFST)
|
||||
|
||||
#define TRANSCEIVERALIGNCNT_REG3 (0xB840)
|
||||
#define TRANSCEIVERALIGNCNT_REG3 (0xC140)
|
||||
|
||||
#define RXALIGNCNTCH3_OFST (0)
|
||||
#define RXALIGNCNTCH3_MSK (0x0000ffff << RXALIGNCNTCH3_OFST)
|
||||
|
||||
#define TRANSCEIVERLASTWORD_REG0 (0xB844)
|
||||
#define TRANSCEIVERLASTWORD_REG0 (0xC144)
|
||||
|
||||
#define RXDATACH0_OFST (0)
|
||||
#define RXDATACH0_MSK (0x0000ffff << RXDATACH0_OFST)
|
||||
|
||||
#define TRANSCEIVERLASTWORD_REG1 (0xB848)
|
||||
#define TRANSCEIVERLASTWORD_REG1 (0xC148)
|
||||
|
||||
#define RXDATACH1_OFST (0)
|
||||
#define RXDATACH1_MSK (0x0000ffff << RXDATACH1_OFST)
|
||||
|
||||
#define TRANSCEIVERLASTWORD_REG2 (0xB84C)
|
||||
#define TRANSCEIVERLASTWORD_REG2 (0xC14C)
|
||||
|
||||
#define RXDATACH2_OFST (0)
|
||||
#define RXDATACH2_MSK (0x0000ffff << RXDATACH2_OFST)
|
||||
|
||||
#define TRANSCEIVERLASTWORD_REG3 (0xB850)
|
||||
#define TRANSCEIVERLASTWORD_REG3 (0xC150)
|
||||
|
||||
#define RXDATACH3_OFST (0)
|
||||
#define RXDATACH3_MSK (0x0000ffff << RXDATACH3_OFST)
|
||||
|
||||
|
||||
// ----------------------------------------------------
|
||||
// TODO: fix these in the firmware reg generator:
|
||||
// ----------------------------------------------------:
|
||||
|
||||
#define DELAY_OUT_REG_1 (0xB054)
|
||||
#define DELAY_OUT_REG_2 (0xB058)
|
||||
#define CYCLES_OUT_REG_1 (0xB05C)
|
||||
#define CYCLES_OUT_REG_2 (0xB060)
|
||||
#define FRAMES_OUT_REG_1 (0xB064)
|
||||
#define FRAMES_OUT_REG_2 (0xB068)
|
||||
#define PERIOD_OUT_REG_1 (0xB06C)
|
||||
#define PERIOD_OUT_REG_2 (0xB070)
|
||||
|
||||
// clang-format on
|
||||
|
||||
Reference in New Issue
Block a user