Pattern unification & Matterhorn Changes (#1303)

* update ctb regDefs, included fill level of adc, transceiver and DBit fifos, added enable registers for cont. readout

* fix fifo fill level range bug

* updated ctb RegDefs, increased size of fifo fill level register

* added register to read the firmware git hash

* ctb: added altchip_id read register

* start with unification of pattern machinery for xctb, ctb, mythen

* udate addrs for d-server internal matterhorn startup

* update xctb reg defs

* move pattern loopdef start

* added zero trimbits to matterhorn config

* Revert "added zero trimbits to matterhorn config"

This reverts commit 7c347badd5.

* added adjustable clocks on Xilinx-CTB

* added support for fractional dividers of runclk

* XCTB: make frequencies adjustable from python gui

* update docs

* added support for patternstart command to XCTB

* XCTB: map pattern_ram directly into memory, removed rw strobe

* refactor Mythen pattern control addresses

* test altera ctb with common addresses, removed ifdefs

* change ordering of regdefs

* updated python help for dbitclk, adcclk and runclk (khz)

* xilinx: moved the wait for firmware to measure the actual frequency to the server side and removed it in the pyctbgui side

* will not be anymore in developer branch

* make format (exception RegisterDefs.h), rewrite XILINX PLL to have less consstants in the code

* bug: mixing && for &

---------

Co-authored-by: Martin Mueller <martin.mueller@psi.ch>
Co-authored-by: Dhanya Thattil <dhanya.thattil@psi.ch>

slsDetectorServers/slsDetectorServer/include/arm64.h

@@ -6,7 +6,9 @@
 #include <sys/types.h>
 
 void bus_w(u_int32_t offset, u_int32_t data);
+void bus_w_csp2(u_int32_t offset, u_int32_t data);
 u_int32_t bus_r(u_int32_t offset);
+u_int32_t bus_r_csp2(u_int32_t offset);
 uint64_t getU64BitReg(int aLSB, int aMSB);
 void setU64BitReg(uint64_t value, int aLSB, int aMSB);
 u_int32_t readRegister(u_int32_t offset);