Pattern unification & Matterhorn Changes (#1303)

* update ctb regDefs, included fill level of adc, transceiver and DBit fifos, added enable registers for cont. readout

* fix fifo fill level range bug

* updated ctb RegDefs, increased size of fifo fill level register

* added register to read the firmware git hash

* ctb: added altchip_id read register

* start with unification of pattern machinery for xctb, ctb, mythen

* udate addrs for d-server internal matterhorn startup

* update xctb reg defs

* move pattern loopdef start

* added zero trimbits to matterhorn config

* Revert "added zero trimbits to matterhorn config"

This reverts commit 7c347badd5.

* added adjustable clocks on Xilinx-CTB

* added support for fractional dividers of runclk

* XCTB: make frequencies adjustable from python gui

* update docs

* added support for patternstart command to XCTB

* XCTB: map pattern_ram directly into memory, removed rw strobe

* refactor Mythen pattern control addresses

* test altera ctb with common addresses, removed ifdefs

* change ordering of regdefs

* updated python help for dbitclk, adcclk and runclk (khz)

* xilinx: moved the wait for firmware to measure the actual frequency to the server side and removed it in the pyctbgui side

* will not be anymore in developer branch

* make format (exception RegisterDefs.h), rewrite XILINX PLL to have less consstants in the code

* bug: mixing && for &

---------

Co-authored-by: Martin Mueller <martin.mueller@psi.ch>
Co-authored-by: Dhanya Thattil <dhanya.thattil@psi.ch>

python/slsdet/detector.py

@@ -3305,7 +3305,11 @@ class Detector(CppDetectorApi):
     @property
     @element
     def runclk(self):
-        """[Ctb] Run clock in MHz."""
+        """
+        [Ctb] Sets Run clock frequency in MHz. \n
+        [Xilinx Ctb] Sets Run clock frequency in kHz.
+        """
+
         return self.getRUNClock()
 
     @runclk.setter
@@ -3386,7 +3390,11 @@ class Detector(CppDetectorApi):
     @property
     @element
     def dbitclk(self):
-        """[Ctb] Clock for latching the digital bits in MHz."""
+        """
+        [Ctb] Sets clock for latching the digital bits in MHz. \n
+        [Xilinx Ctb] clock for latching the digital bits in kHz.
+        """
+
         return self.getDBITClock()
 
     @dbitclk.setter
@@ -3513,7 +3521,11 @@ class Detector(CppDetectorApi):
     @property
     @element
     def adcclk(self):
-        """[Ctb] Sets ADC clock frequency in MHz. """
+        """
+        [Ctb] Sets ADC clock frequency in MHz. \n
+        [Xilinx Ctb] Sets ADC clock frequency in kHz.
+        """
+
         return self.getADCClock()
 
     @adcclk.setter