mirror of
https://github.com/slsdetectorgroup/slsDetectorPackage.git
synced 2025-04-23 06:50:02 +02:00
Merging with anna's jungfrau detector server version
This commit is contained in:
parent
0b1710c267
commit
e7a7dd8c6b
@ -1,6 +1,7 @@
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//#define TESTADC
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#define TESTADC1
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//#define TIMEDBG
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#include "server_defs.h"
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#include "firmware_funcs.h"
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@ -97,7 +98,11 @@ int phase_shift=0;//DEFAULT_PHASE_SHIFT;
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int ipPacketSize=DEFAULT_IP_PACKETSIZE;
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int udpPacketSize=DEFAULT_UDP_PACKETSIZE;
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#ifndef NEW_PLL_RECONFIG
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u_int32_t clkDivider[2]={32,16};
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#else
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u_int32_t clkDivider[2]={40,20};
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#endif
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int32_t clkPhase[2]={0,0};
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u_int32_t adcDisableMask=0;
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@ -436,10 +441,10 @@ void configurePll(int i) {
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// printf("PLL reconfig reset\N"); bus_w(PLL_CNTRL_REG,(1<<PLL_CNTR_RECONFIG_RESET_BIT)); usleep(100); bus_w(PLL_CNTRL_REG, 0);
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#ifndef NEW_PLL_RECONFIG
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printf("PLL mode\n"); setPllReconfigReg(PLL_MODE_REG,1,0);
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// usleep(10000);
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#endif
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if (i<2) {
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@ -496,15 +501,20 @@ void configurePll(int i) {
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// printf("Phase, val: %08x\n", val);
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setPllReconfigReg(PLL_PHASE_SHIFT_REG,val,0); //shifts counter 0
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val=phase | (2<<16);// | (inv<<21);
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#ifndef NEW_PLL_RECONFIG
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printf("Start reconfig\n"); setPllReconfigReg(PLL_START_REG, 1,0);
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// bus_w(PLL_CNTRL_REG, 0);
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printf("Status register\n"); getPllReconfigReg(PLL_STATUS_REG,0);
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// sleep(1);
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printf("PLL mode\n"); setPllReconfigReg(PLL_MODE_REG,1,0);
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// usleep(10000);
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#endif
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printf("**************** phase word %08x\n",val);
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val=phase | (2<<16);// | (inv<<21);
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// printf("Phase, val: %08x\n", val);
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setPllReconfigReg(PLL_PHASE_SHIFT_REG,val,0); //shifts counter 0
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}
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@ -512,12 +522,13 @@ void configurePll(int i) {
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}
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#ifndef NEW_PLL_RECONFIG
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printf("Start reconfig\n"); setPllReconfigReg(PLL_START_REG, 1,0);
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// bus_w(PLL_CNTRL_REG, 0);
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printf("Status register\n"); getPllReconfigReg(PLL_STATUS_REG,0);
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// sleep(1);
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#endif
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// printf("PLL mode\n"); setPllReconfigReg(PLL_MODE_REG,0,0);
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usleep(10000);
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if (i<2) {
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@ -578,13 +589,21 @@ int phaseStep(int st){
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if (st>65535 || st<-65535)
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return clkPhase[0];
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#ifdef NEW_PLL_RECONFIG
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printf("reset pll\n");
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bus_w(PLL_CNTRL_REG,((1<<PLL_CNTR_PLL_RESET_BIT))); //reset PLL
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usleep(100);
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bus_w(PLL_CNTRL_REG, 0);
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printf("phase %d\n", st);
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clkPhase[1]=st;
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#else
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clkPhase[1]=st-clkPhase[0];
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#endif
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printf("phase %d\n", clkPhase[1] );
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configurePll(2);
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clkPhase[0]=st;
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return clkPhase[0];
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@ -1241,7 +1260,7 @@ int64_t setPeriod(int64_t value){
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/* time is in ns */
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if (value!=-1) {
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// value*=(1E-9*CLK_FREQ);
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value*=(1E-3*clkDivider[0]);
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value*=(1E-3*clkDivider[1]);
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}
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if (value%2==0) {
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@ -1264,7 +1283,7 @@ int64_t getPeriod(){
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int64_t setDelay(int64_t value){
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/* time is in ns */
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if (value!=-1) {
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value*=(1E-3*clkDivider[0]);//(1E-9*CLK_FREQ);
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value*=(1E-3*clkDivider[1]);//(1E-9*CLK_FREQ);
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}
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return set64BitReg(value,SET_DELAY_LSB_REG, SET_DELAY_MSB_REG)/(1E-3*clkDivider[0]);//(1E-9*CLK_FREQ);
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}
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@ -1539,52 +1558,60 @@ int getTemperature(int tempSensor, int imod){
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int initHighVoltage(int val, int imod){
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printf("*******SetHV: Doing nothing - still to be implemented!\n");
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/* #ifdef VERBOSE */
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/* printf("Setting/Getting High Voltage of module:%d with val:%d\n",imod,val); */
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/* #endif */
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/* volatile u_int32_t addr=HV_REG; */
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/* int writeVal,writeVal2; */
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/* switch(val){ */
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/* case -1: break; */
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/* case 0: writeVal=0x0; writeVal2=0x0; break; */
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/* case 90: writeVal=0x0; writeVal2=0x1; break; */
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/* case 110:writeVal=0x2; writeVal2=0x3; break; */
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/* case 120:writeVal=0x4; writeVal2=0x5; break; */
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/* case 150:writeVal=0x6; writeVal2=0x7; break; */
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/* case 180:writeVal=0x8; writeVal2=0x9; break; */
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/* case 200:writeVal=0xA; writeVal2=0xB; break; */
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/* default :printf("Invalid voltage\n");return -2;break; */
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/* } */
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/* //to set value */
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/* if(val!=-1){ */
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/* //set value to converted value */
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/* bus_w(addr,writeVal); */
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/* bus_w(addr,writeVal2); */
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/* #ifdef VERBOSE */
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/* printf("Value sent is %d and then %d\n",writeVal,writeVal2); */
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/* #endif */
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/* } */
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/* //read value and return the converted value */
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/* val=bus_r(addr); */
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/* #ifdef VERBOSE */
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/* printf("Value read from reg is %d\n",val); */
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/* #endif */
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/* switch(val){ */
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/* case 0x0:val=0;break; */
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/* case 0x1:val=90;break; */
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/* case 0x3:val=110;break; */
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/* case 0x5:val=120;break; */
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/* case 0x7:val=150;break; */
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/* case 0x9:val=180;break; */
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/* case 0xB:val=200;break; */
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/* default:printf("Weird value read:%d\n",val);return -3;break; */
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/* } */
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/* #ifdef VERBOSE */
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/* printf("High voltage of module:%d is %d\n",imod,val); */
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/* #endif */
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return val;
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u_int32_t offw,codata;
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u_int16_t valw, dacvalue;
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int iru,i,ddx,csdx,cdx;
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float alpha=0.55, fval=val;
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if (val>=0) {
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if (val<60) {
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dacvalue=0;
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val=60;
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} else if (val>=200) {
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dacvalue=0x1;
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val=200;
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} else {
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dacvalue=1.+(200.-val)/alpha;
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val=200.-(dacvalue-1)*alpha;
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}
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printf ("****************************** setting val %d, dacval %d\n",val, dacvalue);
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offw=DAC_REG;
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ddx=8; csdx=10; cdx=9;
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codata=((dacvalue)&0xff);
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valw=0xffff; bus_w(offw,(valw)); // start point
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valw=((valw&(~(0x1<<csdx))));bus_w(offw,valw); //chip sel bar down
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for (i=0;i<8;i++) {
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valw=(valw&(~(0x1<<cdx)));bus_w(offw,valw); //cldwn
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valw=((valw&(~(0x1<<ddx)))+(((codata>>(7-i))&0x1)<<ddx));bus_w(offw,valw);//write data (i)
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valw=((valw&(~(0x1<<cdx)))+(0x1<<cdx));bus_w(offw,valw);//clkup
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}
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valw=((valw&(~(0x1<<csdx)))+(0x1<<csdx));bus_w(offw,valw); //csup
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valw=(valw&(~(0x1<<cdx)));bus_w(offw,valw); //cldwn
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valw=0xffff; bus_w(offw,(valw)); // stop point =start point of course */
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printf("Writing %d in HVDAC \n",dacvalue);
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bus_w(HV_REG,val);
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}
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return bus_r(HV_REG);
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// return val;
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}
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@ -1664,22 +1691,15 @@ int setADC(int adc){
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}
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int configureMAC(uint32_t destip,uint64_t destmac,uint64_t sourcemac,int sourceip,int ival,uint32_t destport) {
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//int configureMAC(int ipad,long long int macad,long long int detectormacad, int detipad, int ival, int udpport){
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uint32_t sourceport = 0x7e9a; // 0xE185;
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long int calcChecksum(int sourceip, int destip) {
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//setheader(0xF452142F3200,0x00ad29ae39fd,0x0a000264,0x0A00020d ,0x8436, 0x7e9a);
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/* void setheader(uint64_t destmac, uint64_t sourcemac, uint32_t destip, uint32_t sourceip, uint32_t destport, */
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/* uint32_t sourceport){ */
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ip_header ip;
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int count;
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unsigned short *addr;
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long int sum = 0;
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long int checksum;
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volatile u_int32_t conf= bus_r(CONFIG_REG);
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ip.ip_ver = 0x4;
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ip.ip_ihl = 0x5;
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@ -1707,7 +1727,61 @@ ip.ip_destip = destip;
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printf("IP checksum is 0x%lx\n",checksum);
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return checksum;
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}
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#ifdef NEW_GBE_INTERFACE
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int writeGbeReg(int ivar, uint32_t val, int addr, int interface) {
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/* #define GBE_CTRL_WSTROBE 0 */
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/* #define GBE_CTRL_VAR_OFFSET 16 */
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/* #define GBE_CTRL_VAR_MASK 0XF */
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/* #define GBE_CTRL_RAMADDR_OFFSET 24 */
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/* #define GBE_CTRL_RAMADDR_MASK 0X3F */
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/* #define GBE_CTRL_INTERFACE 23 */
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uint32_t ctrl=((ivar&GBE_CTRL_VAR_MASK)<<GBE_CTRL_VAR_OFFSET)|((addr&GBE_CTRL_RAMADDR_MASK)<<GBE_CTRL_RAMADDR_OFFSET)| (interface<<GBE_CTRL_INTERFACE);
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bus_w(GBE_CNTRL_REG,ctrl);
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bus_w(GBE_PARAM_REG,val);
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bus_w(GBE_CNTRL_REG,ctrl|(1<<GBE_CTRL_WSTROBE));
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usleep(100);
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bus_w(GBE_CNTRL_REG,ctrl);
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}
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#endif
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int configureInterface(uint32_t destip,uint64_t destmac,uint64_t sourcemac,int sourceip,int ival,uint32_t destport, uint32_t sourceport, int interface) {
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//int configureMAC(int ipad,long long int macad,long long int detectormacad, int detipad, int ival, int udpport){
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volatile u_int32_t conf= bus_r(CONFIG_REG);
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long int checksum=calcChecksum(sourceip, destip);
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#ifdef NEW_GBE_INTERFACE
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printf("Configure interface %d\n",interface);
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const int nvar=12;
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uint32_t vals[nvar];
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int ivar;
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int addr=0;
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vals[RX_UDP_IP_ADDR]=destip;
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vals[RX_UDP_PORTS_ADDR]=destport;
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vals[RX_UDP_MAC_L_ADDR]=(destmac)&0xFFFFFFFF;
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vals[RX_UDP_MAC_H_ADDR]=(destmac>>32)&0xFFFFFFFF;
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vals[IPCHECKSUM_ADDR]=checksum;
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vals[GBE_DELAY_ADDR]=0;
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vals[GBE_RESERVED1_ADDR]=sourceport;
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vals[GBE_RESERVED2_ADDR]=interface;
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vals[DETECTOR_MAC_L_ADDR]=(sourcemac)&0xFFFFFFFF;
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vals[DETECTOR_MAC_H_ADDR]=(sourcemac>>32)&0xFFFFFFFF;
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vals[DETECTOR_IP_ADDR]=sourceip;
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for (ivar=0; ivar<nvar; ivar++) {
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writeGbeReg(ivar, vals[ivar], addr, interface);
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}
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#else
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bus_w(DETECTORIP_AREG,sourceip);//detectorip_AReg_c
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bus_w(RX_UDP_AREG,destip);//rx_udpip_AReg_c
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@ -1718,6 +1792,9 @@ ip.ip_destip = destip;
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bus_w(UDPPORTS_AREG,((sourceport&0xFFFF)<<16)+(destport&0xFFFF));//udpports_AReg_c
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bus_w(IPCHKSUM_AREG,(checksum&0xFFFF));//ipchksum_AReg_c
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#endif
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bus_w(CONTROL_REG,GB10_RESET_BIT);
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sleep(1);
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bus_w(CONTROL_REG,0);
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@ -1726,197 +1803,50 @@ ip.ip_destip = destip;
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printf("System status register is %08x\n",bus_r(SYSTEM_STATUS_REG));
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return 0; //any value doesnt matter - dhanya
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/* } */
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/* #ifdef DDEBUG */
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/* printf("Chip of Intrst Reg:%x\n",bus_r(CHIP_OF_INTRST_REG)); */
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/* printf("IP Packet Size:%d\n",ipPacketSize); */
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/* printf("UDP Packet Size:%d\n",udpPacketSize); */
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/* #endif */
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/* //configuring mac */
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/* u_int32_t addrr=MULTI_PURPOSE_REG; */
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/* u_int32_t offset=ENET_CONF_REG, offset2=TSE_CONF_REG; */
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/* mac_conf *mac_conf_regs; */
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/* tse_conf *tse_conf_regs; */
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/* long int sum = 0; */
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/* long int checksum; */
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/* int count,val; */
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/* unsigned short *addr; */
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/* mac_conf_regs=(mac_conf*)(CSP0BASE+offset*2); */
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/* tse_conf_regs=(tse_conf*)(CSP0BASE+offset2*2); */
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/* #ifdef DDEBUG */
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/* printf("***Configuring MAC*** \n"); */
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/* #endif */
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/* if(ival) */
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/* bus_w(addrr,(RESET_BIT|DIGITAL_TEST_BIT)); //0x080,reset mac (reset) */
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/* else */
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/* bus_w(addrr,RESET_BIT); //0x080,reset mac (reset) */
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/* val=bus_r(addrr); */
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/* #ifdef VERBOSE */
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/* printf("Value read from Multi-purpose Reg:%x\n",val); */
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/* #endif */
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/* // if(val!=0x080) return -1; */
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/* usleep(500000); */
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/* if(ival) */
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/* bus_w(addrr,(ENET_RESETN_BIT|WRITE_BACK_BIT|DIGITAL_TEST_BIT)); //0x840,write shadow regs(enet reset,write bak) */
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/* else */
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/* bus_w(addrr,(ENET_RESETN_BIT|WRITE_BACK_BIT)); //0x840,write shadow regs(enet reset,write bak) */
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/* val=bus_r(addrr); */
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/* #ifdef VERBOSE */
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/* printf("Value read from Multi-purpose Reg:%x\n",val); */
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/* #endif */
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/* // if(val!=0x840) return -1; */
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/* if(ival) */
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/* bus_w(addrr,(ENET_RESETN_BIT|DIGITAL_TEST_BIT)); //0x800,nreset phy(enet reset) */
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/* else */
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/* bus_w(addrr,ENET_RESETN_BIT); //0x800,nreset phy(enet reset) */
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/* val=bus_r(addrr); */
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/* #ifdef VERBOSE */
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/* printf("Value read from Multi-purpose Reg:%x\n",val); */
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/* #endif */
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/* // if(val!=0x800) return -1; */
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/* mac_conf_regs->mac.mac_dest_mac1 =((macad>>(8*5))&0xFF);// 0x00; //pc7060 */
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/* mac_conf_regs->mac.mac_dest_mac2 =((macad>>(8*4))&0xFF);// 0x19; //pc7060 */
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/* mac_conf_regs->mac.mac_dest_mac3 =((macad>>(8*3))&0xFF);// 0x99; //pc7060 */
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/* mac_conf_regs->mac.mac_dest_mac4 =((macad>>(8*2))&0xFF);// 0x24; //pc7060 */
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/* mac_conf_regs->mac.mac_dest_mac5 =((macad>>(8*1))&0xFF);// 0xEB; //pc7060 */
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/* mac_conf_regs->mac.mac_dest_mac6 =((macad>>(8*0))&0xFF);// 0xEE; //pc7060 */
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/* /\* */
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/* mac_conf_regs->mac.mac_src_mac1 = 0x00; */
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/* mac_conf_regs->mac.mac_src_mac2 = 0xAA; */
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/* mac_conf_regs->mac.mac_src_mac3 = 0xBB; */
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/* mac_conf_regs->mac.mac_src_mac4 = 0xCC; */
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/* mac_conf_regs->mac.mac_src_mac5 = 0xDD; */
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/* mac_conf_regs->mac.mac_src_mac6 = 0xEE; */
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/* *\/ */
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/* mac_conf_regs->mac.mac_src_mac1 =((detectormacad>>(8*5))&0xFF); */
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/* mac_conf_regs->mac.mac_src_mac2 =((detectormacad>>(8*4))&0xFF); */
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/* mac_conf_regs->mac.mac_src_mac3 =((detectormacad>>(8*3))&0xFF); */
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/* mac_conf_regs->mac.mac_src_mac4 =((detectormacad>>(8*2))&0xFF); */
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/* mac_conf_regs->mac.mac_src_mac5 =((detectormacad>>(8*1))&0xFF); */
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/* mac_conf_regs->mac.mac_src_mac6 =((detectormacad>>(8*0))&0xFF); */
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/* mac_conf_regs->mac.mac_ether_type = 0x0800; //ipv4 */
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/* mac_conf_regs->ip.ip_ver = 0x4; */
|
||||
/* mac_conf_regs->ip.ip_ihl = 0x5; */
|
||||
/* mac_conf_regs->ip.ip_tos = 0x0; */
|
||||
/* mac_conf_regs->ip.ip_len = ipPacketSize;//0x0522; // was 0x0526; */
|
||||
/* mac_conf_regs->ip.ip_ident = 0x0000; */
|
||||
/* mac_conf_regs->ip.ip_flag = 0x2; */
|
||||
/* mac_conf_regs->ip.ip_offset = 0x00; */
|
||||
/* mac_conf_regs->ip.ip_ttl = 0x70; */
|
||||
/* mac_conf_regs->ip.ip_protocol = 0x11; */
|
||||
/* mac_conf_regs->ip.ip_chksum = 0x0000 ; //6E42 now is automatically computed */
|
||||
/* mac_conf_regs->ip.ip_sourceip = detipad; //0x8181CA2E;129.129.202.46 */
|
||||
/* mac_conf_regs->ip.ip_destip = ipad; //CA57 */
|
||||
|
||||
/* //#ifdef VERBOSE */
|
||||
/* printf("mac_dest:%llx %x:%x:%x:%x:%x:%x\n", */
|
||||
/* macad, */
|
||||
/* mac_conf_regs->mac.mac_dest_mac1, */
|
||||
/* mac_conf_regs->mac.mac_dest_mac2, */
|
||||
/* mac_conf_regs->mac.mac_dest_mac3, */
|
||||
/* mac_conf_regs->mac.mac_dest_mac4, */
|
||||
/* mac_conf_regs->mac.mac_dest_mac5, */
|
||||
/* mac_conf_regs->mac.mac_dest_mac6); */
|
||||
/* printf("mac_src:%llx %x:%x:%x:%x:%x:%x\n", */
|
||||
/* detectormacad, */
|
||||
/* mac_conf_regs->mac.mac_src_mac1, */
|
||||
/* mac_conf_regs->mac.mac_src_mac2, */
|
||||
/* mac_conf_regs->mac.mac_src_mac3, */
|
||||
/* mac_conf_regs->mac.mac_src_mac4, */
|
||||
/* mac_conf_regs->mac.mac_src_mac5, */
|
||||
/* mac_conf_regs->mac.mac_src_mac6); */
|
||||
/* printf("ip_ttl:%x\n",mac_conf_regs->ip.ip_ttl); */
|
||||
/* printf("det_ip: %x %x\n",detipad, mac_conf_regs->ip.ip_sourceip); */
|
||||
/* printf("dest_ip: %x %x\n",ipad, mac_conf_regs->ip.ip_destip); */
|
||||
|
||||
/* //#endif */
|
||||
|
||||
/* //checksum */
|
||||
/* count=sizeof(mac_conf_regs->ip); */
|
||||
/* addr=&(mac_conf_regs->ip); */
|
||||
/* while( count > 1 ) { */
|
||||
/* sum += *addr++; */
|
||||
/* count -= 2; */
|
||||
/* } */
|
||||
/* if( count > 0 ) sum += *addr; // Add left-over byte, if any */
|
||||
/* while (sum>>16) sum = (sum & 0xffff) + (sum >> 16);// Fold 32-bit sum to 16 bits */
|
||||
/* checksum = (~sum)&0xffff; */
|
||||
/* mac_conf_regs->ip.ip_chksum = checksum; */
|
||||
/* //#ifdef VERBOSE */
|
||||
/* printf("IP header checksum is 0x%x s\n",(unsigned int)(checksum)); */
|
||||
/* //#endif */
|
||||
|
||||
/* mac_conf_regs->udp.udp_srcport = 0xE185; */
|
||||
/* mac_conf_regs->udp.udp_destport = udpport;//0xC351; */
|
||||
/* mac_conf_regs->udp.udp_len = udpPacketSize;//0x050E; //was 0x0512; */
|
||||
/* mac_conf_regs->udp.udp_chksum = 0x0000; */
|
||||
|
||||
/* #ifdef VERBOSE */
|
||||
/* printf("Configuring TSE\n"); */
|
||||
/* #endif */
|
||||
/* tse_conf_regs->rev = 0xA00; */
|
||||
/* tse_conf_regs->scratch = 0xCCCCCCCC; */
|
||||
/* tse_conf_regs->command_config = 0xB; */
|
||||
/* tse_conf_regs->mac_0 = 0x17231C00; */
|
||||
/* tse_conf_regs->mac_1 = 0xCB4A; */
|
||||
/* tse_conf_regs->frm_length = 0x5DC; //max frame length (1500 bytes) (was 0x41C) */
|
||||
/* tse_conf_regs->pause_quant = 0x0; */
|
||||
/* tse_conf_regs->rx_section_empty = 0x7F0; */
|
||||
/* tse_conf_regs->rx_section_full = 0x10; */
|
||||
/* tse_conf_regs->tx_section_empty = 0x3F8; //was 0x7F0; */
|
||||
/* tse_conf_regs->tx_section_full = 0x16; */
|
||||
/* tse_conf_regs->rx_almost_empty = 0x8; */
|
||||
/* tse_conf_regs->rx_almost_full = 0x8; */
|
||||
/* tse_conf_regs->tx_almost_empty = 0x8; */
|
||||
/* tse_conf_regs->tx_almost_full = 0x3; */
|
||||
/* tse_conf_regs->mdio_addr0 = 0x12; */
|
||||
/* tse_conf_regs->mdio_addr1 = 0x0; */
|
||||
|
||||
/* mac_conf_regs->cdone = 0xFFFFFFFF; */
|
||||
|
||||
|
||||
/* if(ival) */
|
||||
/* bus_w(addrr,(INT_RSTN_BIT|ENET_RESETN_BIT|WRITE_BACK_BIT|DIGITAL_TEST_BIT)); //0x2840,write shadow regs.. */
|
||||
/* else */
|
||||
/* bus_w(addrr,(INT_RSTN_BIT|ENET_RESETN_BIT|WRITE_BACK_BIT)); //0x2840,write shadow regs.. */
|
||||
|
||||
/* val=bus_r(addrr); */
|
||||
/* #ifdef VERBOSE */
|
||||
/* printf("Value read from Multi-purpose Reg:%x\n",val); */
|
||||
/* #endif */
|
||||
/* // if(val!=0x2840) return -1; */
|
||||
|
||||
/* usleep(100000); */
|
||||
|
||||
/* if(ival) */
|
||||
/* bus_w(addrr,(INT_RSTN_BIT|ENET_RESETN_BIT|SW1_BIT|DIGITAL_TEST_BIT)); //0x2820,write shadow regs.. */
|
||||
/* else */
|
||||
/* bus_w(addrr,(INT_RSTN_BIT|ENET_RESETN_BIT|SW1_BIT)); //0x2820,write shadow regs.. */
|
||||
|
||||
/* val=bus_r(addrr); */
|
||||
/* #ifdef VERBOSE */
|
||||
/* printf("Value read from Multi-purpose Reg:%x\n",val); */
|
||||
/* #endif */
|
||||
/* // if(val!=0x2820) return -1; */
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
||||
/* return adcConfigured; */
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
int configureMAC(uint32_t destip,uint64_t destmac,uint64_t sourcemac,int sourceip,int ival,uint32_t destport) {
|
||||
//int configureMAC(int ipad,long long int macad,long long int detectormacad, int detipad, int ival, int udpport){
|
||||
|
||||
uint32_t sourceport = 0x7e9a; // 0xE185;
|
||||
int interface=0;
|
||||
int ngb;
|
||||
volatile u_int32_t conf= bus_r(CONFIG_REG);
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
#ifdef NEW_GBE_INTERFACE
|
||||
ngb=2;
|
||||
printf("--------- New XGB interface\n");
|
||||
#else
|
||||
ngb=1;
|
||||
printf("********* Old XGB interface\n");
|
||||
#endif
|
||||
|
||||
for (interface=0; interface <ngb; interface++)
|
||||
configureInterface(destip, destmac, sourcemac+interface, sourceip+interface, ival, destport+interface, sourceport+interface, interface);
|
||||
|
||||
|
||||
bus_w(CONTROL_REG,GB10_RESET_BIT);
|
||||
bus_w(CONTROL_REG,0);
|
||||
usleep(10000);
|
||||
bus_w(CONFIG_REG,conf | GB10_NOT_CPU_BIT);
|
||||
printf("System status register is %08x\n",bus_r(SYSTEM_STATUS_REG));
|
||||
return;
|
||||
|
||||
}
|
||||
|
||||
|
||||
|
||||
@ -35,96 +35,6 @@
|
||||
#define ADC_OFFSET_REG 66<<11 //same as ADC_PIPELINE_REG
|
||||
#define ADC_INVERSION_REG 67<<11
|
||||
|
||||
|
||||
|
||||
/* constant FPGAVersionReg_c : integer:= 0; */
|
||||
/* constant FixedPatternReg_c : integer:= 1; */
|
||||
/* constant StatusReg_c : integer:= 2; */
|
||||
/* constant LookAtMeReg_c : integer:= 3; */
|
||||
/* constant SystemStatusReg_c : integer:= 4; */
|
||||
|
||||
/* constant PLL_ParamOutReg_c : integer:=5; -- RO register to check control signals going to the chip */
|
||||
|
||||
|
||||
/* --time registers use only even numbers! */
|
||||
/* constant TimeFromStartReg_c : integer:= 16; */
|
||||
/* --constant TimeFromStartReg_c : integer:= 17; MSB */
|
||||
/* constant GetDelayReg_c : integer:= 18; */
|
||||
/* --constant GetDelayReg_c : integer:= 19; MSB */
|
||||
/* constant GetCyclesReg_c : integer:= 20; */
|
||||
/* --constant GetTrainsReg_c : integer:= 21; MSB */
|
||||
/* constant GetFramesReg_c : integer:= 22; */
|
||||
/* --constant GetFramesReg_c : integer:= 23; MSB */
|
||||
/* constant GetPeriodReg_c : integer:= 24; */
|
||||
/* --constant GetPeriodReg_c : integer:= 25; MSB */
|
||||
/* constant GetExpTimeReg_c : integer:= 26; */
|
||||
/* --constant GetExpTimeReg_c : integer:= 27; MSB */
|
||||
/* constant GetGatesReg_c : integer:= 28; */
|
||||
/* --constant GetGatesReg_c : integer:= 29; MSB */
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
/* -----rw: */
|
||||
|
||||
/* constant DACReg_c : integer:= 64; */
|
||||
/* constant ADCWriteReg_c : integer:= 65; */
|
||||
/* constant ADCsyncReg_c : integer:= 66; */
|
||||
/* constant HVReg_c : integer:= 67; */
|
||||
/* constant DummyReg_c : integer:= 68; */
|
||||
|
||||
/* constant rx_udpip_AReg_c : integer:= 69; */
|
||||
/* constant udpports_AReg_c : integer:= 70; */
|
||||
/* constant rx_udpmacL_AReg_c : integer:= 71; */
|
||||
/* constant rx_udpmacH_AReg_c : integer:= 72; */
|
||||
/* constant detectormacL_AReg_c : integer:= 73; */
|
||||
/* constant detectormacH_AReg_c : integer:= 74; */
|
||||
/* constant detectorip_AReg_c : integer:= 75; */
|
||||
/* constant ipchksum_AReg_c : integer:= 76; */
|
||||
|
||||
/* constant ConfigReg_c : integer:= 77; */
|
||||
/* constant ExtSignalReg_c : integer:= 78; */
|
||||
/* constant ControlReg_c : integer:= 79; */
|
||||
|
||||
|
||||
|
||||
/* constant PLL_ParamReg_c : integer:= 80; */
|
||||
/* constant PLL_CntrlReg_c : integer:=81; */
|
||||
|
||||
|
||||
|
||||
|
||||
/* --time registers use only even numbers! */
|
||||
/* -- DELAY_AFTER_TRIGGER, */
|
||||
/* constant SetDelayReg_c : integer:= 96; */
|
||||
/* --constant SetDelayReg_c : integer:= 97; MSB */
|
||||
/* -- CYCLES_NUMBER, */
|
||||
/* constant SetCyclesReg_c : integer:= 98; */
|
||||
/* --constant SetCyclesReg_c : integer:= 99;MSB */
|
||||
/* -- FRAME_NUMBER, */
|
||||
/* constant SetFramesReg_c : integer:= 100; */
|
||||
/* --constant SetFramesReg_c : integer:= 101; MSB */
|
||||
/* -- FRAME_PERIOD, */
|
||||
/* constant SetPeriodReg_c : integer:= 102; */
|
||||
/* --constant SetPeriodReg_c : integer:= 103; MSB */
|
||||
/* -- ACQUISITION_TIME, */
|
||||
/* constant SetExpTimeReg_c : integer:= 104; */
|
||||
/* --constant SetExpTimeReg_c : integer:= 105; MSB */
|
||||
/* -- GATES_NUMBER, */
|
||||
/* constant SetGatesReg_c : integer:= 106; */
|
||||
/* --constant SetGatesReg_c : integer:= 107; MSB */
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
#define DAC_REG 64<<11//0x17<<11// control the dacs
|
||||
//ADC
|
||||
#define ADC_WRITE_REG 65<<11//0x18<<11
|
||||
@ -238,17 +148,22 @@
|
||||
#define PLL_CNTRL_REG 81<<11//0x34<<11
|
||||
|
||||
|
||||
#ifdef NEW_GBE_INTERFACE
|
||||
#define GBE_PARAM_OUT_REG 40<<11
|
||||
#define GBE_PARAM_REG 69<<11
|
||||
#define GBE_CNTRL_REG 70<<11
|
||||
#else
|
||||
#define RX_UDP_AREG 69<<11 //rx_udpip_AReg_c : integer:= 69; *\/
|
||||
#define UDPPORTS_AREG 70<<11// udpports_AReg_c : integer:= 70; *\/
|
||||
#define RX_UDPMACL_AREG 71<<11//rx_udpmacL_AReg_c : integer:= 71; *\/
|
||||
#define RX_UDPMACH_AREG 72<<11//rx_udpmacH_AReg_c : integer:= 72; *\/
|
||||
#define DETECTORMACL_AREG 73<<11//detectormacL_AReg_c : integer:= 73; *\/
|
||||
#define DETECTORMACH_AREG 74<<11//detectormacH_AReg_c : integer:= 74; *\/
|
||||
#define DETECTORIP_AREG 75<<11//detectorip_AReg_c : integer:= 75; *\/
|
||||
#define IPCHKSUM_AREG 76<<11//ipchksum_AReg_c : integer:= 76; *\/ */
|
||||
#endif
|
||||
|
||||
|
||||
#define RX_UDP_AREG 69<<11 //rx_udpip_AReg_c : integer:= 69; */
|
||||
#define UDPPORTS_AREG 70<<11// udpports_AReg_c : integer:= 70; */
|
||||
#define RX_UDPMACL_AREG 71<<11//rx_udpmacL_AReg_c : integer:= 71; */
|
||||
#define RX_UDPMACH_AREG 72<<11//rx_udpmacH_AReg_c : integer:= 72; */
|
||||
#define DETECTORMACL_AREG 73<<11//detectormacL_AReg_c : integer:= 73; */
|
||||
#define DETECTORMACH_AREG 74<<11//detectormacH_AReg_c : integer:= 74; */
|
||||
#define DETECTORIP_AREG 75<<11//detectorip_AReg_c : integer:= 75; */
|
||||
#define IPCHKSUM_AREG 76<<11//ipchksum_AReg_c : integer:= 76; */
|
||||
|
||||
#define PATTERN_CNTRL_REG 82<<11
|
||||
#define PATTERN_LIMITS_AREG 83<<11
|
||||
|
||||
@ -270,6 +185,7 @@
|
||||
#define DAQ_REG 93<<11
|
||||
#define ADC_LATCH_DISABLE_REG 94<<11
|
||||
|
||||
#define HV_REG 95<<11
|
||||
|
||||
#define PATTERN_IOCTRL_REG_LSB 108<<11
|
||||
#define PATTERN_IOCTRL_REG_MSB 109<<11
|
||||
@ -382,14 +298,16 @@
|
||||
#define READSTATE_0_BIT 0x00000100
|
||||
#define READSTATE_1_BIT 0x00000200
|
||||
#define READSTATE_2_BIT 0x00000400
|
||||
#define PLL_RECONFIG_BUSY 0x00100000
|
||||
#define SOME_FIFO_FULL_BIT 0x00000800 // error!
|
||||
|
||||
#define RUNSTATE_0_BIT 0x00001000
|
||||
#define RUNSTATE_1_BIT 0x00002000
|
||||
#define RUNSTATE_2_BIT 0x00004000
|
||||
#define SOME_FIFO_FULL_BIT 0x00008000 // error!
|
||||
#define STOPPED_BIT 0x00008000 // error!
|
||||
#define ALL_FIFO_EMPTY_BIT 0x00010000 // data ready
|
||||
#define RUNMACHINE_BUSY_BIT 0x00020000
|
||||
#define READMACHINE_BUSY_BIT 0x00040000
|
||||
#define PLL_RECONFIG_BUSY 0x00100000
|
||||
|
||||
|
||||
|
||||
@ -551,8 +469,40 @@
|
||||
#define PPL_BW_PARAM_DEFAULT 0x2EE0
|
||||
#define PPL_VCO_PARAM_DEFAULT 0x1
|
||||
|
||||
#define PLL_VCO_FREQ_MHZ 480//800
|
||||
#define NEW_PLL_RECONFIG
|
||||
|
||||
#ifdef NEW_PLL_RECONFIG
|
||||
#define PLL_VCO_FREQ_MHZ 400//480//800
|
||||
#else
|
||||
#define PLL_VCO_FREQ_MHZ 480//800
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
/*
|
||||
GBE parameter and control registers definitions
|
||||
*/
|
||||
|
||||
#define GBE_CTRL_WSTROBE 0
|
||||
#define GBE_CTRL_VAR_OFFSET 16
|
||||
#define GBE_CTRL_VAR_MASK 0XF
|
||||
#define GBE_CTRL_RAMADDR_OFFSET 24
|
||||
#define GBE_CTRL_RAMADDR_MASK 0X3F
|
||||
#define GBE_CTRL_INTERFACE 23
|
||||
|
||||
#define RX_UDP_IP_ADDR 0
|
||||
#define RX_UDP_PORTS_ADDR 1
|
||||
#define RX_UDP_MAC_L_ADDR 2
|
||||
#define RX_UDP_MAC_H_ADDR 3
|
||||
#define IPCHECKSUM_ADDR 4
|
||||
#define GBE_DELAY_ADDR 5
|
||||
#define GBE_RESERVED1_ADDR 6
|
||||
#define GBE_RESERVED2_ADDR 7
|
||||
#define DETECTOR_MAC_L_ADDR 8
|
||||
#define DETECTOR_MAC_H_ADDR 9
|
||||
#define DETECTOR_IP_ADDR 10
|
||||
|
||||
|
||||
|
||||
|
||||
@ -1079,7 +1079,6 @@ int set_dac(int file_des) {
|
||||
ret=FAIL;
|
||||
sprintf(mess,"Detector locked by %s\n",lastClientIP);
|
||||
} else{
|
||||
|
||||
if (ind<16) {
|
||||
|
||||
if (mV) {
|
||||
@ -1109,21 +1108,13 @@ int set_dac(int file_des) {
|
||||
}
|
||||
retval=adcvpp;;
|
||||
|
||||
}
|
||||
} else if (ind==HV_NEW )
|
||||
retval=initHighVoltageByModule(val,imod);
|
||||
else
|
||||
printf("**********No dac with index %d\n",ind);
|
||||
}
|
||||
}
|
||||
if(ret==OK){
|
||||
/* ret=FAIL; */
|
||||
/* if(idac==HIGH_VOLTAGE){ */
|
||||
/* if(retval==-2) */
|
||||
/* strcpy(mess,"Invalid Voltage.Valid values are 0,90,110,120,150,180,200"); */
|
||||
/* else if(retval==-3) */
|
||||
/* strcpy(mess,"Weird value read back or it has not been set yet\n"); */
|
||||
/* else */
|
||||
/* ret=OK; */
|
||||
/* }//since v r saving only msb */
|
||||
/* else if ((retval-val)<=3 || val==-1) */
|
||||
/* ret=OK; */
|
||||
if (ind<16) {
|
||||
if (mV) {
|
||||
|
||||
@ -1132,8 +1123,9 @@ int set_dac(int file_des) {
|
||||
printf("%d mV \n",retval1);
|
||||
} else
|
||||
retval1=retval;
|
||||
}
|
||||
}
|
||||
} else
|
||||
retval1=retval;
|
||||
|
||||
#endif
|
||||
|
||||
#ifdef VERBOSE
|
||||
@ -2000,10 +1992,13 @@ int get_run_status(int file_des) {
|
||||
// else if(!(retval&RUNMACHINE_BUSY_BIT)){ //commented by Anna 24.10.2012
|
||||
else if(!(retval&RUN_BUSY_BIT)){ // by Anna 24.10.2012
|
||||
|
||||
if((retval&STOPPED_BIT) ){ //
|
||||
|
||||
|
||||
//and readbusy=1, its last frame read
|
||||
if((retval&READMACHINE_BUSY_BIT) ){ //
|
||||
printf("-----------------------------------STOPPED--------------------------\n");
|
||||
s=STOPPED;
|
||||
} else if((retval&READMACHINE_BUSY_BIT) ){ // ///and readbusy=1, its last frame read
|
||||
|
||||
|
||||
|
||||
printf("-----------------------------------READ MACHINE BUSY--------------------------\n");
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user