mirror of
https://github.com/slsdetectorgroup/slsDetectorPackage.git
synced 2025-06-23 10:07:59 +02:00
moench and eiger updated as well
This commit is contained in:
@ -219,6 +219,8 @@
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#define PLL_CNTRL_WR_PRMTR_MSK (0x00000001 << PLL_CNTRL_WR_PRMTR_OFST)
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#define PLL_CNTRL_PLL_RST_OFST (3)
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#define PLL_CNTRL_PLL_RST_MSK (0x00000001 << PLL_CNTRL_PLL_RST_OFST)
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#define PLL_CNTRL_DBIT_WR_PRMTR_OFST (5)
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#define PLL_CNTRL_DBIT_WR_PRMTR_MSK (0x00000001 << PLL_CNTRL_DBIT_WR_PRMTR_OFST)
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#define PLL_CNTRL_ADDR_OFST (16)
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#define PLL_CNTRL_ADDR_MSK (0x0000003F << PLL_CNTRL_ADDR_OFST)
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Binary file not shown.
@ -38,7 +38,7 @@ int virtual_stop = 0;
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enum detectorSettings thisSettings = UNINITIALIZED;
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int highvoltage = 0;
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int dacValues[NDAC] = {};
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int adcPhase = 0;
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int32_t clkPhase[NUM_CLOCKS] = {};
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int detPos[4] = {};
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int numUDPInterfaces = 1;
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@ -366,7 +366,12 @@ void initStopServer() {
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void setupDetector() {
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FILE_LOG(logINFO, ("This Server is for 1 Jungfrau module (500k)\n"));
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adcPhase = 0;
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{
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int i = 0;
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for (i = 0; i < NUM_CLOCKS; ++i) {
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clkPhase[i] = 0;
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}
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}
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ALTERA_PLL_ResetPLL();
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resetCore();
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resetPeripheral();
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@ -389,7 +394,7 @@ void setupDetector() {
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setDefaultDacs();
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// altera pll
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ALTERA_PLL_SetDefines(PLL_CNTRL_REG, PLL_PARAM_REG, PLL_CNTRL_RCNFG_PRMTR_RST_MSK, PLL_CNTRL_WR_PRMTR_MSK, PLL_CNTRL_PLL_RST_MSK, PLL_CNTRL_ADDR_MSK, PLL_CNTRL_ADDR_OFST);
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ALTERA_PLL_SetDefines(PLL_CNTRL_REG, PLL_PARAM_REG, PLL_CNTRL_RCNFG_PRMTR_RST_MSK, PLL_CNTRL_WR_PRMTR_MSK, PLL_CNTRL_PLL_RST_MSK, PLL_CNTRL_ADDR_MSK, PLL_CNTRL_ADDR_OFST, PLL_CNTRL_DBIT_WR_PRMTR_MSK, DBIT_CLK_INDEX);
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bus_w(DAQ_REG, 0x0); /* Only once at server startup */
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@ -1390,12 +1395,13 @@ int getClockDivider(enum CLKINDEX ind) {
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}
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int setPhase(enum CLKINDEX ind, int val, int degrees){
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if (ind != ADC_CLK) {
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if (ind != ADC_CLK && ind != DBIT_CLK) {
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FILE_LOG(logERROR, ("Unknown clock index %d to set phase\n", ind));
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return FAIL;
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}
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char* clock_names[] = {CLK_NAMES};
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FILE_LOG(logINFO, ("Setting %s clock (%d) phase to %d %s\n", clock_names[ind], ind, val, degrees == 0 ? "" : "degrees"));
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int maxShift = MAX_PHASE_SHIFTS;
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// validation
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if (degrees && (val < 0 || val > 359)) {
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FILE_LOG(logERROR, ("\tPhase provided outside limits (0 - 359°C)\n"));
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@ -1406,7 +1412,6 @@ int setPhase(enum CLKINDEX ind, int val, int degrees){
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return FAIL;
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}
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FILE_LOG(logINFO, ("Setting ADC Phase to %d (degree mode: %d)\n", val, degrees));
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int valShift = val;
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// convert to phase shift
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if (degrees) {
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@ -1414,14 +1419,15 @@ int setPhase(enum CLKINDEX ind, int val, int degrees){
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}
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FILE_LOG(logDEBUG1, ("phase shift: %d (degrees/shift: %d)\n", valShift, val));
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int relativePhase = valShift - adcPhase;
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FILE_LOG(logDEBUG1, ("relative phase shift: %d (Current phase: %d)\n", relativePhase, adcPhase));
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int relativePhase = valShift - clkPhase[ind];
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FILE_LOG(logDEBUG1, ("relative phase shift: %d (Current phase: %d)\n", relativePhase, clkPhase[ind]));
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// same phase
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if (!relativePhase) {
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FILE_LOG(logINFO, ("Nothing to do in Phase Shift\n"));
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return OK;
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}
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FILE_LOG(logINFOBLUE, ("Configuring Phase\n"));
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int phase = 0;
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if (relativePhase > 0) {
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@ -1431,29 +1437,29 @@ int setPhase(enum CLKINDEX ind, int val, int degrees){
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}
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FILE_LOG(logDEBUG1, ("[Single Direction] Phase:%d (0x%x). Max Phase shifts:%d\n", phase, phase, maxShift));
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ALTERA_PLL_SetPhaseShift(phase, 1, 0);
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ALTERA_PLL_SetPhaseShift(phase, (ind == ADC_CLK ? ADC_CLK_INDEX : DBIT_CLK_INDEX), 0);
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adcPhase = valShift;
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clkPhase[ind] = valShift;
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alignDeserializer();
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return OK;
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}
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int getPhase(enum CLKINDEX ind, int degrees) {
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if (ind != ADC_CLK) {
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if (ind != ADC_CLK && ind != DBIT_CLK) {
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FILE_LOG(logERROR, ("Unknown clock index %d to get phase\n", ind));
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return -1;
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}
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if (!degrees)
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return adcPhase;
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return clkPhase[ind];
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// convert back to degrees
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int val = 0;
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ConvertToDifferentRange(0, MAX_PHASE_SHIFTS - 1, 0, 359, adcPhase, &val);
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ConvertToDifferentRange(0, MAX_PHASE_SHIFTS - 1, 0, 359, clkPhase[ind], &val);
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return val;
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}
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int getMaxPhase(enum CLKINDEX ind) {
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if (ind != ADC_CLK) {
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if (ind != ADC_CLK && ind != DBIT_CLK) {
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FILE_LOG(logERROR, ("Unknown clock index %d to get max phase\n", ind));
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return -1;
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}
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@ -1461,7 +1467,7 @@ int getMaxPhase(enum CLKINDEX ind) {
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}
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int validatePhaseinDegrees(enum CLKINDEX ind, int val, int retval) {
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if (ind != ADC_CLK) {
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if (ind != ADC_CLK && ind != DBIT_CLK) {
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FILE_LOG(logERROR, ("Unknown clock index %d to validate phase in degrees\n", ind));
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return FAIL;
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}
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@ -4,7 +4,7 @@
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#define MIN_REQRD_VRSN_T_RD_API 0x171220
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#define REQRD_FRMWRE_VRSN_BOARD2 0x190716
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#define REQRD_FRMWRE_VRSN_BOARD2 0x200304
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#define REQRD_FRMWRE_VRSN 0x190708
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#define CTRL_SRVR_INIT_TIME_US (300 * 1000)
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@ -50,8 +50,8 @@ enum DACINDEX {J_VB_COMP, J_VDD_PROT, J_VIN_COM, J_VREF_PRECH, J_VB_PIXBUF, J
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420 /* J_VREF_COMP */ \
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};
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enum NETWORKINDEX { TXN_FRAME, FLOWCTRL_10G };
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enum CLKINDEX {RUN_CLK, ADC_CLK, NUM_CLOCKS};
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#define CLK_NAMES "run", "adc"
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enum CLKINDEX {RUN_CLK, ADC_CLK, DBIT_CLK, NUM_CLOCKS};
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#define CLK_NAMES "run", "adc", "dbit"
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/* Hardware Definitions */
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#define NCHAN (256 * 256)
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@ -63,6 +63,8 @@ enum CLKINDEX {RUN_CLK, ADC_CLK, NUM_CLOCKS};
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#define DATA_BYTES (NCHIP * NCHAN * NUM_BYTES_PER_PIXEL)
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#define CLK_RUN (40) /* MHz */
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#define CLK_SYNC (20) /* MHz */
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#define ADC_CLK_INDEX (1)
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#define DBIT_CLK_INDEX (0)
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/** Default Parameters */
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#define DEFAULT_NUM_FRAMES (100*1000*1000)
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