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binaries in and updated api versioning
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@@ -59,13 +59,13 @@
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#define DEFAULT_SYSTEM_C2 (5) //(144444448) // sync_clk, 144 MHz
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#define DEFAULT_SYSTEM_C3 (5) //(144444448) // str_clk, 144 MHz
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#define DEFAULT_READOUT_SPEED (G_108MHz)
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#define DEFAULT_READOUT_SPEED (G_108MHZ)
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#define SPEED_144_CLKDIV_0 (6)
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#define SPEED_144_CLKDIV_1 (6)
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#define SPEED_144_CLKPHASE_DEG_1 (125)
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#define SPEED_144_CLKPHASE_DEG_1 (122) // 125 not possible
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#define SPEED_108_CLKDIV_0 (8)
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#define SPEED_108_CLKDIV_1 (8)
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#define SPEED_108_CLKPHASE_DEG_1 (270)
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#define SPEED_108_CLKPHASE_DEG_1 (268) // 270 not possible
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/* Firmware Definitions */
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#define FIXED_PLL_FREQUENCY (20000000) // 20MHz
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