detectors/slsDetectorPackage
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binaries in and updated api versioning

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This commit is contained in:
maliakal_d
2021-10-07 19:11:37 +02:00
parent 6b0e6a72df
commit e3e3639829
17 changed files with 75 additions and 53 deletions
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BIN
slsDetectorServers/gotthard2DetectorServer/bin/gotthard2DetectorServer_developer
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Binary file not shown.

38
slsDetectorServers/gotthard2DetectorServer/slsDetectorFunctionList.c
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@ -506,6 +506,7 @@ void setupDetector() {
setCurrentSource(DEFAULT_CURRENT_SOURCE);
setVetoAlgorithm(DEFAULT_ALGORITHM, LOW_LATENCY_LINK);
setVetoAlgorithm(DEFAULT_ALGORITHM, ETHERNET_10GB);
setReadoutSpeed(DEFAULT_READOUT_SPEED);
}
void setASICDefaults() {
@ -2084,7 +2085,36 @@ int getVCOFrequency(enum CLKINDEX ind) {
}
int setReadoutSpeed(int val) {
switch (val)
switch (val) {
case G_108MHZ:
LOG(logINFOBLUE, ("Setting readout speed to 108 MHz\n"));
if (setClockDivider(READOUT_C0, SPEED_108_CLKDIV_0) == FAIL) {
return FAIL;
}
if (setClockDivider(READOUT_C1, SPEED_108_CLKDIV_1) == FAIL) {
return FAIL;
}
if (setPhase(READOUT_C1, SPEED_108_CLKPHASE_DEG_1, 1) == FAIL) {
return FAIL;
}
break;
case G_144MHZ:
LOG(logINFOBLUE, ("Setting readout speed to 144 MHz\n"));
if (setClockDivider(READOUT_C0, SPEED_144_CLKDIV_0) == FAIL) {
return FAIL;
}
if (setClockDivider(READOUT_C1, SPEED_144_CLKDIV_1) == FAIL) {
return FAIL;
}
if (setPhase(READOUT_C1, SPEED_144_CLKPHASE_DEG_1, 1) == FAIL) {
return FAIL;
}
break;
default:
LOG(logERROR, ("Unknown readout speed %d\n", val));
return FAIL;
}
return OK;
}
int getReadoutSpeed(int* retval) {
@ -2092,13 +2122,13 @@ int getReadoutSpeed(int* retval) {
// clkdiv 2, 3, 4, 5?
if (clkDivider[READOUT_C0] == SPEED_108_CLKDIV_0 &&
clkDivider[READOUT_C1] == SPEED_108_CLKDIV_1 &&
getPhase(READOUT_C0, 1) == SPEED_108_CLKPHASE_DEG_1) {
getPhase(READOUT_C1, 1) == SPEED_108_CLKPHASE_DEG_1) {
*retval = G_108MHZ;
}
else if (clkDivider[READOUT_C0] == SPEED_144_CLKDIV_0 &&
clkDivider[READOUT_C1] == SPEED_144_CLKDIV_1 &&
getPhase(READOUT_C0, 1) == SPEED_144_CLKPHASE_DEG_1) {
getPhase(READOUT_C1, 1) == SPEED_144_CLKPHASE_DEG_1) {
*retval = G_144MHZ;
}
@ -2121,7 +2151,7 @@ int setClockDivider(enum CLKINDEX ind, int val) {
}
char *clock_names[] = {CLK_NAMES};
LOG(logINFO, ("\tSetting %s clock (%d) divider from %d to %d\n",
LOG(logINFOBLUE, ("Setting %s clock (%d) divider from %d to %d\n",
clock_names[ind], ind, clkDivider[ind], val));
// Remembering old phases in degrees

6
slsDetectorServers/gotthard2DetectorServer/slsDetectorServer_defs.h
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@ -59,13 +59,13 @@
#define DEFAULT_SYSTEM_C2 (5) //(144444448) // sync_clk, 144 MHz
#define DEFAULT_SYSTEM_C3 (5) //(144444448) // str_clk, 144 MHz
#define DEFAULT_READOUT_SPEED (G_108MHz)
#define DEFAULT_READOUT_SPEED (G_108MHZ)
#define SPEED_144_CLKDIV_0 (6)
#define SPEED_144_CLKDIV_1 (6)
#define SPEED_144_CLKPHASE_DEG_1 (125)
#define SPEED_144_CLKPHASE_DEG_1 (122) // 125 not possible
#define SPEED_108_CLKDIV_0 (8)
#define SPEED_108_CLKDIV_1 (8)
#define SPEED_108_CLKPHASE_DEG_1 (270)
#define SPEED_108_CLKPHASE_DEG_1 (268) // 270 not possible
/* Firmware Definitions */
#define FIXED_PLL_FREQUENCY (20000000) // 20MHz