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m3: changed run clk div to 10, change run clkdiv to 40 while trimming, set default pipeline adif reg

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maliakal_d
2020-10-09 16:52:24 +02:00
parent 2bd796cfff
commit e364fbcf32
4 changed files with 61 additions and 7 deletions
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10
slsDetectorServers/mythen3DetectorServer/RegisterDefs.h
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@@ -148,6 +148,16 @@
#define DTA_OFFSET_REG (0x24 * REG_OFFSET + BASE_CONTROL)
/* Formatting for adif core -----------------------------------------------*/
#define ADIF_CONFIG_REG (0x00 * REG_OFFSET + BASE_ADIF)
#define ADIF_ADDTNL_OFST_OFST (0)
#define ADIF_ADDTNL_OFST_MSK (0x00000003 << ADIF_ADDTNL_OFST_OFST)
#define ADIF_PIPELINE_OFST (4)
#define ADIF_PIPELINE_MSK (0x0000000F << ADIF_PIPELINE_OFST)
/* Formatting for data core -----------------------------------------------*/
#define FMT_CONFIG_REG (0x00 * REG_OFFSET + BASE_FMT)