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mythen3: numcounters to mask, updating gateperiod

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This commit is contained in:
maliakal_d 2020-06-08 10:15:10 +02:00
parent 6c95bf171b
commit e306c39e1d
2 changed files with 18 additions and 63 deletions
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11
slsDetectorServers/mythen3DetectorServer/RegisterDefs.h
View File

@ -104,12 +104,11 @@
/* Config RW regiseter */
#define CONFIG_REG (0x20 * REG_OFFSET + BASE_CONTROL)
#define CONFIG_COUNTER_ENA_OFST (0)
#define CONFIG_COUNTER_ENA_MSK (0x00000003 << CONFIG_COUNTER_ENA_OFST)
#define CONFIG_COUNTER_ENA_DEFAULT_VAL ((0x0 << CONFIG_COUNTER_ENA_OFST) & CONFIG_COUNTER_ENA_MSK)
#define CONFIG_COUNTER_ENA_1_VAL ((0x1 << CONFIG_COUNTER_ENA_OFST) & CONFIG_COUNTER_ENA_MSK)
#define CONFIG_COUNTER_ENA_2_VAL ((0x2 << CONFIG_COUNTER_ENA_OFST) & CONFIG_COUNTER_ENA_MSK)
#define CONFIG_COUNTER_ENA_ALL_VAL ((0x3 << CONFIG_COUNTER_ENA_OFST) & CONFIG_COUNTER_ENA_MSK)
#define CONFIG_COUNTERS_ENA_OFST (0)
#define CONFIG_COUNTERS_ENA_MSK (0x00000007 << CONFIG_COUNTERS_ENA_OFST)
#define CONFIG_COUNTER_1_ENA_VAL ((0x1 << CONFIG_COUNTERS_ENA_OFST) & CONFIG_COUNTERS_ENA_MSK)
#define CONFIG_COUNTER_2_ENA_VAL ((0x2 << CONFIG_COUNTERS_ENA_OFST) & CONFIG_COUNTERS_ENA_MSK)
#define CONFIG_COUNTER_3_ENA_VAL ((0x4 << CONFIG_COUNTERS_ENA_OFST) & CONFIG_COUNTERS_ENA_MSK)
#define CONFIG_DYNAMIC_RANGE_OFST (4)
#define CONFIG_DYNAMIC_RANGE_MSK (0x00000003 << CONFIG_DYNAMIC_RANGE_OFST)
#define CONFIG_DYNAMIC_RANGE_1_VAL ((0x0 << CONFIG_DYNAMIC_RANGE_OFST) & CONFIG_DYNAMIC_RANGE_MSK)

70
slsDetectorServers/mythen3DetectorServer/slsDetectorFunctionList.c
View File

@ -49,8 +49,6 @@ uint32_t clkDivider[NUM_CLOCKS] = {};
int highvoltage = 0;
int detPos[2] = {};
uint32_t countermask =
0; // will be removed later when in firmware converted to mask
int isInitCheckDone() { return initCheckDone; }
@ -851,11 +849,14 @@ int getNumGates() { return bus_r(ASIC_EXP_EXT_GATE_NUMBER_REG); }
void updateGatePeriod() {
uint64_t max = 0;
uint32_t countermask = getCounterMask();
for (int i = 0; i != 3; ++i) {
// TODO: only those counters enabled (when updated to mask in firmware)
uint64_t sum = getExpTime(i) + getGateDelay(i);
if (sum > max) {
max = sum;
// only if counter enabled
if ((1 << i) & countermask) {
uint64_t sum = getExpTime(i) + getGateDelay(i);
if (sum > max) {
max = sum;
}
}
}
LOG(logINFO, ("\tSetting Gate Period to %lld ns\n", (long long int)max));
@ -1004,64 +1005,19 @@ void setCounterMask(uint32_t arg) {
if (arg == 0 || arg > MAX_COUNTER_MSK) {
return;
}
countermask = arg;
// convert mask into number of counters (until firmware converts to mask)
int ncounters = __builtin_popcount(countermask);
LOG(logINFO, ("Setting number of counters to %d\n", ncounters));
uint32_t val = 0;
switch (ncounters) {
case 1:
val = CONFIG_COUNTER_ENA_1_VAL;
break;
case 2:
val = CONFIG_COUNTER_ENA_2_VAL;
break;
default:
val = CONFIG_COUNTER_ENA_ALL_VAL;
break;
}
LOG(logINFO, ("Setting counter mask to 0x%x\n", arg));
uint32_t addr = CONFIG_REG;
bus_w(addr, bus_r(addr) & ~CONFIG_COUNTER_ENA_MSK);
bus_w(addr, bus_r(addr) | val);
bus_w(addr, bus_r(addr) & ~CONFIG_COUNTERS_ENA_MSK);
bus_w(addr, bus_r(addr) | ((arg << CONFIG_COUNTERS_ENA_OFST) &
CONFIG_COUNTERS_ENA_MSK));
LOG(logDEBUG, ("Config Reg: 0x%x\n", bus_r(addr)));
updateGatePeriod();
}
uint32_t getCounterMask() {
uint32_t addr = CONFIG_REG;
uint32_t regval = (bus_r(addr) & CONFIG_COUNTER_ENA_MSK);
int ncounters = 0;
switch (regval) {
case CONFIG_COUNTER_ENA_1_VAL:
ncounters = 1;
break;
case CONFIG_COUNTER_ENA_2_VAL:
ncounters = 2;
break;
default:
ncounters = 3;
break;
}
// confirm ncounters work with mask saved in server (until firmware converts
// to mask)
int nc = __builtin_popcount(countermask);
// if not equal, make a mask of what is in register (will change once
// firmware changes)
if (nc != ncounters) {
switch (ncounters) {
case 1:
countermask = 0x1;
break;
case 2:
countermask = 0x3;
break;
default:
countermask = 0x7;
break;
}
}
return countermask;
return ((bus_r(CONFIG_REG) & CONFIG_COUNTERS_ENA_MSK) >>
CONFIG_COUNTERS_ENA_OFST);
}
int setDelayAfterTrigger(int64_t val) {