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https://github.com/slsdetectorgroup/slsDetectorPackage.git
synced 2025-06-23 10:07:59 +02:00
add missing commands and cleanup
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@ -232,7 +232,7 @@ It is normally recommended to use \verb=sls\_detector\_acquire [j-]=, which take
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%\item[checkonline]
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%\item[readctr i fname] GOTTHARD related - reads counter in detector to file fname, restarts acquisition if i=1
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\item[resetctr i] GOTTHARD- ADVANCED- resets counter in detector, restarts acquisition if i=1
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\item[resmat 1] \E - ADVANCED - resets counter in detector before each acquisition. Default settings. \textit{resmat 0} does not reset the counter bit before the acquisition. Note that in \E the counter is always reset after the acquisition.
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\item[resmat i] \E - ADVANCED - resets counter in detector before the following acquisition. Default settings is \textit{resmat 1}. \textit{resmat 0} does not reset the counter bit before the acquisition. Note that in \E the counter is always reset after the acquisition.
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%\item[exptimel]
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%\item[periodl]
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%\item[delayl]
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@ -248,7 +248,7 @@ It is normally recommended to use \verb=sls\_detector\_acquire [j-]=, which take
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\subsubsection{Configuration}
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Advanced commands to configure the detector system. Should be left to the configuration file
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\begin{description}
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\item[type s] Sets the types of detector controllers in the system. Can be Mythen, Gotthard, Eiger and multiple controllers should be catenated with a + (e.g. Mythen+Mythen for 2 Mythen controllers).
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\item[type s] Sets the types of detector controllers in the system. Can be Mythen, Gotthard, \E and multiple controllers should be catenated with a + (e.g. Mythen+Mythen for 2 Mythen controllers).
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\item[d:hostname s] Sets the hostname or IP address for the controller d, where d is the controller index within the detector structure.
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\item[d:extsig:i s] Configures the usage of the external IO signals to synchronize the detectors. s can be: off, gate\_in\_active\_high, gate\_in\_active\_low, trigger\_in\_rising\_edge,
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trigger\_in\_falling\_edge,
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@ -375,7 +375,7 @@ Advanced settings changing the analog or digital performance of the acquisition.
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%\item[temp\_adc n] Sets
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%\item[temp\_fpga n]
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\item[reg a d] Write to register of address a the data d
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\item[clkdivider n] Sets the clock divider for the readout. Can be increased for longer cables. For EIGER options are 0 (full speed), 1 (half speed), 2 (quarter speed), and 3 (slow).
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\item[clkdivider n] Sets the clock divider for the readout. Can be increased for longer cables. For \E options are 0 (full speed), 1 (half speed), 2 (quarter speed), and 3 (slow).
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\item[setlength n] Changes the length of the set/reset signals in the acquisition. Never reduce it!
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\item[waitstates n] Sets the wait states for CPU/FPGA communication. Do not change it!
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\item[totdivider n] Sets the tot clock divider.
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